Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
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Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_endpoint_err_req_cg 100.00 1 100 1 64 64




Group Instance : edn_endpoint_err_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_endpoint_err_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance edn_endpoint_err_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
endpoint_cg 7 0 7 100.00 100 1 1 0


Summary for Variable endpoint_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for endpoint_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
range[0x0] 525 1 T16 136 T20 70 T21 116
range[0x1] 534 1 T16 129 T20 59 T21 139
range[0x2] 505 1 T16 131 T20 63 T21 134
range[0x3] 512 1 T16 130 T20 66 T21 128
range[0x4] 522 1 T16 137 T20 67 T21 122
range[0x5] 533 1 T16 131 T20 67 T21 131
range[0x6] 548 1 T16 129 T20 70 T21 132

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%