Group : tb.dut.u_edn_cov_if::edn_error_cg
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Group : tb.dut.u_edn_cov_if::edn_error_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
75.00 75.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_error_cg 75.00 1 100 1 64 64




Group Instance : edn_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance edn_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 2 6 75.00


Variables for Group Instance edn_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error_test 8 2 6 75.00 100 1 1 0


Summary for Variable cp_error_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 2 6 75.00


Automatically Generated Bins for cp_error_test

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[EdnFifoWriteErrTest] 0 1 1
auto[EdnFifoReadErrTest] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[EdnSfifoRescmdErrTest] 26 1 T16 6 T20 3 T21 6
auto[EdnSfifoGencmdErrTest] 27 1 T16 5 T20 2 T21 8
auto[EdnAckSmErrTest] 1140 1 T6 1 T16 260 T19 1
auto[EdnMainSmErrTest] 1140 1 T6 1 T16 260 T19 1
auto[EdnCntrErrTest] 115 1 T16 20 T20 10 T21 20
auto[EdnFifoStateErrTest] 53 1 T16 11 T20 5 T21 14

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