Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181026	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

383651

1

T1

9

T2

9

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	239916	1			T1	47		T2	66		T3	58
values[0x0]	153108	1			T1	4		T2	5		T3	13
values[0x1]	171653	1			T1	3		T2	5		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

444069

1

T1

24

T2

30

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3962	1			T2	2		T4	2		T27	2
valid_sources[0x01]	1732	1			T4	2		T16	1		T41	2
valid_sources[0x02]	2278	1			T16	2		T32	1		T91	4
valid_sources[0x03]	1859	1			T1	2		T4	1		T27	1
valid_sources[0x04]	2786	1			T4	3		T16	2		T18	1
valid_sources[0x05]	1899	1			T2	1		T4	1		T16	7
valid_sources[0x06]	2327	1			T2	2		T16	1		T12	2
valid_sources[0x07]	2249	1			T4	1		T16	6		T29	5
valid_sources[0x08]	2684	1			T4	4		T16	7		T64	1
valid_sources[0x09]	1753	1			T16	6		T41	2		T75	3
valid_sources[0x0a]	2555	1			T16	1		T65	1		T32	1
valid_sources[0x0b]	2299	1			T10	5		T16	4		T64	1
valid_sources[0x0c]	2291	1			T63	1		T16	9		T11	9
valid_sources[0x0d]	2371	1			T16	3		T29	2		T64	1
valid_sources[0x0e]	1853	1			T4	2		T25	2		T27	1
valid_sources[0x0f]	2491	1			T29	2		T41	1		T91	3
valid_sources[0x10]	1666	1			T16	1		T64	1		T41	2
valid_sources[0x11]	2016	1			T4	1		T63	1		T16	5
valid_sources[0x12]	2157	1			T2	1		T16	2		T32	2
valid_sources[0x13]	2341	1			T4	3		T16	8		T64	1
valid_sources[0x14]	2037	1			T4	3		T16	4		T29	1
valid_sources[0x15]	1725	1			T2	1		T16	1		T28	1
valid_sources[0x16]	2891	1			T4	1		T16	2		T64	1
valid_sources[0x17]	2216	1			T4	1		T16	11		T12	2
valid_sources[0x18]	1737	1			T4	2		T16	6		T12	3
valid_sources[0x19]	1997	1			T4	3		T16	3		T28	1
valid_sources[0x1a]	1813	1			T4	3		T16	3		T28	1
valid_sources[0x1b]	1808	1			T2	1		T4	2		T27	1
valid_sources[0x1c]	1965	1			T4	1		T27	1		T16	2
valid_sources[0x1d]	1744	1			T4	2		T63	2		T16	4
valid_sources[0x1e]	2514	1			T4	1		T16	1		T28	1
valid_sources[0x1f]	1738	1			T4	2		T16	6		T65	2
valid_sources[0x20]	2376	1			T16	1		T57	1		T20	3
valid_sources[0x21]	1894	1			T2	2		T4	1		T6	5
valid_sources[0x22]	1980	1			T4	3		T26	2		T16	3
valid_sources[0x23]	2330	1			T4	1		T63	1		T16	4
valid_sources[0x24]	2397	1			T4	2		T16	4		T41	1
valid_sources[0x25]	2414	1			T4	3		T16	6		T11	1
valid_sources[0x26]	2357	1			T4	1		T16	2		T29	2
valid_sources[0x27]	1916	1			T2	1		T4	1		T16	3
valid_sources[0x28]	2023	1			T4	1		T63	1		T30	5
valid_sources[0x29]	2360	1			T2	1		T4	1		T16	4
valid_sources[0x2a]	2092	1			T4	1		T16	5		T29	3
valid_sources[0x2b]	1906	1			T4	3		T16	5		T18	1
valid_sources[0x2c]	2075	1			T27	1		T16	1		T64	1
valid_sources[0x2d]	2425	1			T4	3		T10	3		T63	1
valid_sources[0x2e]	1934	1			T2	1		T4	4		T16	4
valid_sources[0x2f]	2695	1			T16	3		T64	1		T30	3
valid_sources[0x30]	2404	1			T4	2		T16	4		T64	2
valid_sources[0x31]	2293	1			T10	15		T16	2		T18	3
valid_sources[0x32]	2047	1			T2	2		T16	2		T28	1
valid_sources[0x33]	1993	1			T16	2		T41	1		T91	4
valid_sources[0x34]	1986	1			T2	1		T4	3		T16	4
valid_sources[0x35]	1768	1			T4	1		T16	3		T29	2
valid_sources[0x36]	1918	1			T16	4		T19	5		T41	3
valid_sources[0x37]	2053	1			T4	2		T64	1		T65	2
valid_sources[0x38]	2589	1			T2	1		T25	3		T27	1
valid_sources[0x39]	2984	1			T5	31		T16	3		T64	1
valid_sources[0x3a]	2159	1			T63	1		T16	7		T29	4
valid_sources[0x3b]	2253	1			T16	5		T29	1		T12	4
valid_sources[0x3c]	2967	1			T1	4		T4	2		T16	2
valid_sources[0x3d]	2165	1			T2	1		T26	2		T16	3
valid_sources[0x3e]	2177	1			T4	4		T16	2		T19	5
valid_sources[0x3f]	1625	1			T4	5		T16	5		T29	1
valid_sources[0x40]	3047	1			T2	1		T4	2		T16	2
valid_sources[0x41]	2209	1			T16	9		T32	1		T41	1
valid_sources[0x42]	1711	1			T4	3		T27	1		T10	1
valid_sources[0x43]	2409	1			T2	2		T4	2		T63	1
valid_sources[0x44]	2841	1			T4	1		T16	6		T41	1
valid_sources[0x45]	1806	1			T4	2		T16	2		T64	1
valid_sources[0x46]	2098	1			T1	2		T63	1		T16	3
valid_sources[0x47]	2460	1			T4	1		T16	1		T91	4
valid_sources[0x48]	2620	1			T16	1		T41	1		T20	2
valid_sources[0x49]	2037	1			T4	3		T16	5		T64	1
valid_sources[0x4a]	2133	1			T4	2		T16	4		T29	5
valid_sources[0x4b]	2322	1			T1	2		T16	3		T64	2
valid_sources[0x4c]	2276	1			T1	1		T2	1		T4	1
valid_sources[0x4d]	1790	1			T27	2		T63	1		T16	3
valid_sources[0x4e]	1974	1			T16	2		T64	2		T41	7
valid_sources[0x4f]	2321	1			T2	2		T4	1		T26	1
valid_sources[0x50]	1886	1			T4	7		T16	7		T29	1
valid_sources[0x51]	2551	1			T2	1		T4	2		T27	1
valid_sources[0x52]	1866	1			T4	1		T16	3		T76	1
valid_sources[0x53]	1958	1			T4	2		T27	1		T16	3
valid_sources[0x54]	2020	1			T4	1		T16	3		T64	1
valid_sources[0x55]	1708	1			T16	12		T76	1		T20	2
valid_sources[0x56]	2189	1			T16	1		T40	1		T41	1
valid_sources[0x57]	2017	1			T4	2		T27	1		T10	3
valid_sources[0x58]	1976	1			T16	3		T29	1		T64	1
valid_sources[0x59]	2015	1			T4	4		T10	2		T16	7
valid_sources[0x5a]	2165	1			T4	1		T16	2		T28	1
valid_sources[0x5b]	2310	1			T4	3		T27	1		T16	2
valid_sources[0x5c]	2354	1			T2	1		T63	1		T16	2
valid_sources[0x5d]	2617	1			T4	1		T16	1		T28	2
valid_sources[0x5e]	2420	1			T2	2		T4	1		T16	5
valid_sources[0x5f]	2377	1			T4	1		T27	1		T16	2
valid_sources[0x60]	2898	1			T2	2		T16	6		T29	2
valid_sources[0x61]	2411	1			T1	4		T4	2		T16	3
valid_sources[0x62]	1966	1			T2	1		T4	1		T27	1
valid_sources[0x63]	2733	1			T4	1		T16	1		T64	1
valid_sources[0x64]	1892	1			T16	3		T91	2		T57	1
valid_sources[0x65]	2119	1			T1	2		T4	5		T16	4
valid_sources[0x66]	2239	1			T4	2		T6	2		T16	5
valid_sources[0x67]	1786	1			T4	1		T16	3		T18	2
valid_sources[0x68]	2427	1			T2	2		T27	1		T16	5
valid_sources[0x69]	1730	1			T16	4		T29	4		T41	3
valid_sources[0x6a]	2110	1			T16	8		T29	3		T32	1
valid_sources[0x6b]	2187	1			T4	2		T16	2		T11	6
valid_sources[0x6c]	1916	1			T1	2		T4	1		T27	1
valid_sources[0x6d]	1758	1			T16	4		T11	6		T12	1
valid_sources[0x6e]	2163	1			T4	3		T16	4		T64	2
valid_sources[0x6f]	2437	1			T1	1		T4	2		T16	4
valid_sources[0x70]	1972	1			T2	1		T4	1		T16	8
valid_sources[0x71]	1776	1			T1	1		T2	4		T4	2
valid_sources[0x72]	2295	1			T1	1		T2	1		T4	1
valid_sources[0x73]	2078	1			T2	1		T16	3		T12	1
valid_sources[0x74]	1756	1			T16	4		T29	4		T12	1
valid_sources[0x75]	2257	1			T2	1		T16	1		T28	2
valid_sources[0x76]	1761	1			T2	1		T4	1		T16	2
valid_sources[0x77]	2055	1			T4	5		T16	4		T41	1
valid_sources[0x78]	2306	1			T4	2		T16	6		T41	2
valid_sources[0x79]	2561	1			T16	3		T29	1		T41	1
valid_sources[0x7a]	1926	1			T16	3		T65	4		T32	1
valid_sources[0x7b]	2225	1			T4	2		T16	5		T65	2
valid_sources[0x7c]	2631	1			T4	1		T27	1		T10	3
valid_sources[0x7d]	1938	1			T2	1		T4	3		T27	1
valid_sources[0x7e]	1919	1			T4	3		T27	8		T16	3
valid_sources[0x7f]	2157	1			T2	1		T16	1		T29	1
valid_sources[0x80]	1826	1			T2	2		T16	1		T64	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103523

1

T1

5

T2

4

T3

7

values[0x0]

all_enables

biggest_size

140994

1

T1

3

T2

3

T3

12

values[0x1]

all_enables

biggest_size

139134

1

T1

1

T2

2

T3

17