Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1921	1			T3	1		T4	4		T10	7
non_zero_bins[1]	1320	1			T3	2		T4	2		T29	2
zero	6980	1			T1	3		T2	3		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	327	1			T56	1		T57	1		T110	1
uni	2551	1			T1	1		T2	1		T3	1
gen	3360	1			T1	1		T2	1		T3	1
res	687	1			T3	1		T4	2		T10	3
ins	3296	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6619

1

T1

3

T2

3

T3

2

mubi_true

3602

1

T3

2

T4

5

T25

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

37

1

T18

1

T87

1

T127

1

pass

10184

1

T1

3

T2

3

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	91	1			T112	1		T49	1		T116	1
upd	non_zero_bins[0]	pass	mubi_true	63	1			T112	1		T305	1		T116	2
upd	non_zero_bins[1]	pass	mubi_false	56	1			T56	1		T57	1		T110	1
upd	non_zero_bins[1]	pass	mubi_true	48	1			T116	1		T306	2		T307	1
upd	zero	pass	mubi_false	37	1			T117	1		T262	1		T236	3
upd	zero	pass	mubi_true	32	1			T125	1		T262	1		T308	1
uni	zero	pass	mubi_false	1932	1			T1	1		T2	1		T3	1
uni	zero	pass	mubi_true	619	1			T4	2		T63	1		T28	1
gen	non_zero_bins[0]	pass	mubi_false	389	1			T3	1		T4	1		T56	1
gen	non_zero_bins[0]	pass	mubi_true	344	1			T10	3		T110	1		T71	1
gen	non_zero_bins[1]	pass	mubi_false	231	1			T4	1		T91	1		T110	2
gen	non_zero_bins[1]	pass	mubi_true	233	1			T29	1		T64	1		T56	1
gen	zero	fail	mubi_false	33	1			T18	1		T87	1		T127	1
gen	zero	pass	mubi_false	1424	1			T1	1		T2	1		T4	4
gen	zero	pass	mubi_true	706	1			T25	1		T27	2		T6	2
res	non_zero_bins[0]	pass	mubi_false	149	1			T10	3		T12	1		T110	1
res	non_zero_bins[0]	pass	mubi_true	173	1			T4	1		T41	1		T22	2
res	non_zero_bins[1]	pass	mubi_false	107	1			T4	1		T48	1		T23	3
res	non_zero_bins[1]	pass	mubi_true	108	1			T3	1		T13	2		T52	3
res	zero	fail	mubi_false	4	1			T178	1		T180	1		T309	1
res	zero	pass	mubi_false	79	1			T91	1		T43	5		T110	1
res	zero	pass	mubi_true	67	1			T11	2		T12	2		T122	1
ins	non_zero_bins[0]	pass	mubi_false	352	1			T12	1		T91	1		T57	1
ins	non_zero_bins[0]	pass	mubi_true	360	1			T4	2		T10	1		T29	1
ins	non_zero_bins[1]	pass	mubi_false	267	1			T64	1		T56	1		T110	1
ins	non_zero_bins[1]	pass	mubi_true	270	1			T3	1		T29	1		T11	1
ins	zero	pass	mubi_false	1468	1			T1	1		T2	1		T4	4
ins	zero	pass	mubi_true	579	1			T25	2		T27	1		T6	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded