Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 100.00 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.71 100.00 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.31 100.00 91.03 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  73 1/1 fifo_pop_o = 1'b1; Tests: T1 T2 T3  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T1 T2 T3  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  80 1/1 state_d = AckPls; Tests: T1 T2 T3  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T1 T2 T3  85 1/1 state_d = Idle; Tests: T1 T2 T3  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T83,T208
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T11,T45,T86
DataWait->Error 99 Covered T40,T70,T111
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T1,T2,T3
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T19,T40


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 90706238 995798 0 0
FpvSecCmErrorStEscalate_A 90706238 1003981 0 0
u_state_regs_A 90661123 89345907 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 90706238 995798 0 0
T5 9905 4522 0 0
T6 19369 6909 0 0
T7 0 7440 0 0
T10 14819 0 0 0
T16 313761 108465 0 0
T17 0 2226 0 0
T19 3325 1350 0 0
T20 0 48832 0 0
T28 7210 0 0 0
T29 27181 0 0 0
T40 0 7937 0 0
T63 9401 0 0 0
T64 42364 0 0 0
T65 7742 0 0 0
T70 0 4270 0 0
T111 0 8008 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 90706238 1003981 0 0
T5 9905 4529 0 0
T6 19369 6916 0 0
T7 0 7447 0 0
T10 14819 0 0 0
T16 313761 110285 0 0
T17 0 2233 0 0
T19 3325 1357 0 0
T20 0 49742 0 0
T28 7210 0 0 0
T29 27181 0 0 0
T40 0 7944 0 0
T63 9401 0 0 0
T64 42364 0 0 0
T65 7742 0 0 0
T70 0 4277 0 0
T111 0 8015 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 90661123 89345907 0 0
T1 6629 5936 0 0
T2 6783 6146 0 0
T3 25704 25340 0 0
T4 75509 73122 0 0
T5 9749 8853 0 0
T6 18168 17076 0 0
T10 14819 14441 0 0
T25 7973 7413 0 0
T26 8029 7441 0 0
T27 15869 15351 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T42 T41 T13  73 1/1 fifo_pop_o = 1'b1; Tests: T42 T41 T13  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T42 T41 T13  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T42 T41 T13  80 1/1 state_d = AckPls; Tests: T42 T41 T13  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T42 T41 T13  85 1/1 state_d = Idle; Tests: T42 T41 T13  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 11 78.57
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T42,T41,T13
DataWait 75 Covered T42,T41,T13
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T42,T41,T13
DataWait->AckPls 80 Covered T42,T41,T13
DataWait->Disabled 107 Not Covered
DataWait->Error 99 Covered T217,T214,T218
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T42,T41,T13
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T42,T41,T13
Idle - 1 0 - Covered T42,T41,T13
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T42,T41,T13
DataWait - - - 0 Covered T42,T41,T13
AckPls - - - - Covered T42,T41,T13
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T20,T21


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 142564 0 0
FpvSecCmErrorStEscalate_A 12958034 143733 0 0
u_state_regs_A 12958034 12770146 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 142564 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1070 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 200 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1141 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 143733 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1071 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 201 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1142 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 12770146 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1415 1287 0 0
T6 2767 2611 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  73 1/1 fifo_pop_o = 1'b1; Tests: T1 T2 T3  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T1 T2 T3  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T1 T2 T3  80 1/1 state_d = AckPls; Tests: T1 T2 T3  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T1 T2 T3  85 1/1 state_d = Idle; Tests: T1 T2 T3  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T1,T2,T3
DataWait 75 Covered T1,T2,T3
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T2,T3
DataWait->AckPls 80 Covered T1,T2,T3
DataWait->Disabled 107 Covered T86,T37,T38
DataWait->Error 99 Covered T61,T153,T219
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T2,T3
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T2,T3
Idle - 1 0 - Covered T1,T2,T3
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T2,T3
DataWait - - - 0 Covered T1,T2,T3
AckPls - - - - Covered T1,T2,T3
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T19,T40


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 140414 0 0
FpvSecCmErrorStEscalate_A 12958034 141583 0 0
u_state_regs_A 12912919 12725031 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 140414 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1020 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 150 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1091 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 141583 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1021 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 151 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1092 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12912919 12725031 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1259 1131 0 0
T6 1566 1410 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T11 T40 T41  73 1/1 fifo_pop_o = 1'b1; Tests: T11 T41 T43  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T11 T40 T41  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T11 T40 T41  80 1/1 state_d = AckPls; Tests: T11 T41 T43  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T11 T41 T43  85 1/1 state_d = Idle; Tests: T11 T41 T43  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T11,T41,T43
DataWait 75 Covered T11,T40,T41
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T11,T41,T43
DataWait->AckPls 80 Covered T11,T41,T43
DataWait->Disabled 107 Covered T11,T220
DataWait->Error 99 Covered T40,T111,T193
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T11,T40,T41
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T11,T41,T43
Idle - 1 0 - Covered T11,T40,T41
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T11,T41,T43
DataWait - - - 0 Covered T11,T40,T41
AckPls - - - - Covered T11,T41,T43
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T20,T21


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 142564 0 0
FpvSecCmErrorStEscalate_A 12958034 143733 0 0
u_state_regs_A 12958034 12770146 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 142564 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1070 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 200 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1141 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 143733 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1071 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 201 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1142 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 12770146 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1415 1287 0 0
T6 2767 2611 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T41 T47 T46  73 1/1 fifo_pop_o = 1'b1; Tests: T41 T47 T46  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T41 T47 T46  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T41 T47 T46  80 1/1 state_d = AckPls; Tests: T41 T47 T46  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T41 T47 T46  85 1/1 state_d = Idle; Tests: T41 T47 T46  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T41,T47,T46
DataWait 75 Covered T41,T47,T46
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T41,T47,T46
DataWait->AckPls 80 Covered T41,T47,T46
DataWait->Disabled 107 Covered T92,T174
DataWait->Error 99 Covered T8,T140,T158
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T41,T47,T46
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T41,T47,T46
Idle - 1 0 - Covered T41,T47,T46
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T41,T47,T46
DataWait - - - 0 Covered T41,T46,T13
AckPls - - - - Covered T41,T47,T46
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T20,T21


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 142564 0 0
FpvSecCmErrorStEscalate_A 12958034 143733 0 0
u_state_regs_A 12958034 12770146 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 142564 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1070 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 200 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1141 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 143733 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1071 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 201 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1142 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 12770146 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1415 1287 0 0
T6 2767 2611 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T25 T10 T6  73 1/1 fifo_pop_o = 1'b1; Tests: T25 T10 T12  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T25 T10 T6  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T25 T10 T6  80 1/1 state_d = AckPls; Tests: T25 T10 T12  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T25 T10 T12  85 1/1 state_d = Idle; Tests: T25 T10 T12  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T25,T10,T12
DataWait 75 Covered T25,T10,T6
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T25,T10,T12
DataWait->AckPls 80 Covered T25,T10,T12
DataWait->Disabled 107 Covered T25,T12,T93
DataWait->Error 99 Covered T6,T221,T222
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T25,T10,T6
Idle->Disabled 107 Covered T4,T27,T10
Idle->Error 99 Covered T5,T16,T19



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T25,T10,T12
Idle - 1 0 - Covered T25,T10,T6
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T25,T10,T12
DataWait - - - 0 Covered T25,T10,T6
AckPls - - - - Covered T25,T10,T12
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T20,T21


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 142564 0 0
FpvSecCmErrorStEscalate_A 12958034 143733 0 0
u_state_regs_A 12958034 12770146 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 142564 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1070 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 200 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1141 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 143733 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1071 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 201 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1142 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 12770146 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1415 1287 0 0
T6 2767 2611 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T27 T5 T45  73 1/1 fifo_pop_o = 1'b1; Tests: T27 T5 T45  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T27 T5 T45  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T27 T5 T45  80 1/1 state_d = AckPls; Tests: T27 T5 T45  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T27 T5 T45  85 1/1 state_d = Idle; Tests: T27 T5 T45  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T27,T5,T45
DataWait 75 Covered T27,T5,T45
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T208
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T27,T5,T45
DataWait->AckPls 80 Covered T27,T5,T45
DataWait->Disabled 107 Covered T45,T173,T223
DataWait->Error 99 Covered T70,T224,T225
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T27,T5,T45
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T27,T5,T45
Idle - 1 0 - Covered T27,T5,T45
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T27,T5,T45
DataWait - - - 0 Covered T27,T45,T30
AckPls - - - - Covered T27,T5,T45
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T20,T21


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 142564 0 0
FpvSecCmErrorStEscalate_A 12958034 143733 0 0
u_state_regs_A 12958034 12770146 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 142564 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1070 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 200 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1141 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 143733 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1071 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 201 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1142 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 12770146 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1415 1287 0 0
T6 2767 2611 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00

51 52 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled): 52.1 `ifdef SIMULATION 52.2 prim_sparse_fsm_flop #( 52.3 .StateEnumT(state_e), 52.4 .Width($bits(state_e)), 52.5 .ResetValue($bits(state_e)'(Disabled)), 52.6 .EnableAlertTriggerSVA(1), 52.7 .CustomForceName("state_q") 52.8 ) u_state_regs ( 52.9 .clk_i ( clk_i ), 52.10 .rst_ni ( rst_ni ), 52.11 .state_i ( state_d ), 52.12 .state_o ( ) 52.13 ); 52.14 always_ff @(posedge clk_i or negedge rst_ni) begin 52.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3  52.16 1/1 state_q <= Disabled; Tests: T1 T2 T3  52.17 end else begin 52.18 1/1 state_q <= state_d; Tests: T1 T2 T3  52.19 end 52.20 end 52.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 52.22 else begin 52.23 `ifdef UVM 52.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 52.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1); 52.26 `else 52.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 52.28 `PRIM_STRINGIFY(u_state_regs_A)); 52.29 `endif 52.30 end 52.31 `else 52.32 prim_sparse_fsm_flop #( 52.33 .StateEnumT(state_e), 52.34 .Width($bits(state_e)), 52.35 .ResetValue($bits(state_e)'(Disabled)), 52.36 .EnableAlertTriggerSVA(1) 52.37 ) u_state_regs ( 52.38 .clk_i ( `PRIM_FLOP_CLK ), 52.39 .rst_ni ( `PRIM_FLOP_RST ), 52.40 .state_i ( state_d ), 52.41 .state_o ( state_q ) 52.42 ); 52.43 `endif53 54 always_comb begin 55 1/1 state_d = state_q; Tests: T1 T2 T3  56 1/1 ack_o = 1'b0; Tests: T1 T2 T3  57 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3  58 1/1 fifo_pop_o = 1'b0; Tests: T1 T2 T3  59 1/1 ack_sm_err_o = 1'b0; Tests: T1 T2 T3  60 1/1 unique case (state_q) Tests: T1 T2 T3  61 Disabled: begin 62 1/1 if (enable_i) begin Tests: T1 T2 T3  63 1/1 state_d = EndPointClear; Tests: T1 T2 T3  64 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3  65 end MISSING_ELSE 66 end 67 EndPointClear: begin 68 1/1 state_d = Idle; Tests: T1 T2 T3  69 end 70 Idle: begin 71 1/1 if (req_i) begin Tests: T1 T2 T3  72 1/1 if (fifo_not_empty_i) begin Tests: T12 T41 T17  73 1/1 fifo_pop_o = 1'b1; Tests: T12 T41 T17  74 end MISSING_ELSE 75 1/1 state_d = DataWait; Tests: T12 T41 T17  76 end MISSING_ELSE 77 end 78 DataWait: begin 79 1/1 if (fifo_not_empty_i) begin Tests: T12 T41 T17  80 1/1 state_d = AckPls; Tests: T12 T41 T17  81 end MISSING_ELSE 82 end 83 AckPls: begin 84 1/1 ack_o = 1'b1; Tests: T12 T41 T17  85 1/1 state_d = Idle; Tests: T12 T41 T17  86 end 87 Error: begin 88 1/1 ack_sm_err_o = 1'b1; Tests: T5 T6 T16  89 end 90 default: begin 91 ack_sm_err_o = 1'b1; 92 state_d = Error; 93 end 94 endcase // unique case (state_q) 95 96 // If local escalation is seen, transition directly to 97 // error state. 98 1/1 if (local_escalate_i) begin Tests: T1 T2 T3  99 1/1 state_d = Error; Tests: T5 T6 T16  100 // Tie off outputs, except for ack_sm_err_o. 101 1/1 ack_o = 1'b0; Tests: T5 T6 T16  102 1/1 fifo_clr_o = 1'b0; Tests: T5 T6 T16  103 1/1 fifo_pop_o = 1'b0; Tests: T5 T6 T16  104 1/1 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin Tests: T1 T2 T3  105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 1/1 state_d = Disabled; Tests: T25 T27 T10  108 // Tie off all outputs, except for ack_sm_err_o. 109 1/1 ack_o = 1'b0; Tests: T25 T27 T10  110 1/1 fifo_pop_o = 1'b0; Tests: T25 T27 T10  111 1/1 fifo_clr_o = 1'b0; Tests: T25 T27 T10  112 end MISSING_ELSE

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT25,T27,T10

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
AckPls 80 Covered T12,T41,T17
DataWait 75 Covered T12,T41,T17
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T5,T6,T16
Idle 68 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
AckPls->Disabled 107 Covered T83
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T12,T41,T17
DataWait->AckPls 80 Covered T12,T41,T17
DataWait->Disabled 107 Covered T85,T226,T141
DataWait->Error 99 Covered T227,T139,T215
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T20,T21
EndPointClear->Disabled 107 Covered T10,T43,T99
EndPointClear->Error 99 Covered T16,T20,T21
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T12,T41,T17
Idle->Disabled 107 Covered T4,T25,T27
Idle->Error 99 Covered T5,T6,T16



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00


52 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


60 unique case (state_q) -1- 61 Disabled: begin 62 if (enable_i) begin -2- 63 state_d = EndPointClear; ==> 64 fifo_clr_o = 1'b1; 65 end MISSING_ELSE ==> 66 end 67 EndPointClear: begin 68 state_d = Idle; ==> 69 end 70 Idle: begin 71 if (req_i) begin -3- 72 if (fifo_not_empty_i) begin -4- 73 fifo_pop_o = 1'b1; ==> 74 end MISSING_ELSE ==> 75 state_d = DataWait; 76 end MISSING_ELSE ==> 77 end 78 DataWait: begin 79 if (fifo_not_empty_i) begin -5- 80 state_d = AckPls; ==> 81 end MISSING_ELSE ==> 82 end 83 AckPls: begin 84 ack_o = 1'b1; ==> 85 state_d = Idle; 86 end 87 Error: begin 88 ack_sm_err_o = 1'b1; ==> 89 end 90 default: begin 91 ack_sm_err_o = 1'b1; ==>

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T12,T41,T17
Idle - 1 0 - Covered T12,T41,T17
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T12,T41,T17
DataWait - - - 0 Covered T12,T41,T46
AckPls - - - - Covered T12,T41,T17
Error - - - - Covered T5,T6,T16
default - - - - Covered T16,T20,T21


98 if (local_escalate_i) begin -1- 99 state_d = Error; ==> 100 // Tie off outputs, except for ack_sm_err_o. 101 ack_o = 1'b0; 102 fifo_clr_o = 1'b0; 103 fifo_pop_o = 1'b0; 104 end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin -2- 105 // Only disable if state is legal and not Disabled or Error. 106 // Even when disabled, illegal states must result in a transition to Error. 107 state_d = Disabled; ==> 108 // Tie off all outputs, except for ack_sm_err_o. 109 ack_o = 1'b0; 110 fifo_pop_o = 1'b0; 111 fifo_clr_o = 1'b0; 112 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T16
0 1 Covered T25,T27,T10
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
AckSmErrorStStable_A 12958034 142564 0 0
FpvSecCmErrorStEscalate_A 12958034 143733 0 0
u_state_regs_A 12958034 12770146 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 142564 0 0
T5 1415 646 0 0
T6 2767 987 0 0
T7 0 1070 0 0
T10 2117 0 0 0
T16 44823 15495 0 0
T17 0 318 0 0
T19 475 200 0 0
T20 0 6976 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1141 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 610 0 0
T111 0 1144 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 143733 0 0
T5 1415 647 0 0
T6 2767 988 0 0
T7 0 1071 0 0
T10 2117 0 0 0
T16 44823 15755 0 0
T17 0 319 0 0
T19 475 201 0 0
T20 0 7106 0 0
T28 1030 0 0 0
T29 3883 0 0 0
T40 0 1142 0 0
T63 1343 0 0 0
T64 6052 0 0 0
T65 1106 0 0 0
T70 0 611 0 0
T111 0 1145 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12958034 12770146 0 0
T1 947 848 0 0
T2 969 878 0 0
T3 3672 3620 0 0
T4 10787 10446 0 0
T5 1415 1287 0 0
T6 2767 2611 0 0
T10 2117 2063 0 0
T25 1139 1059 0 0
T26 1147 1063 0 0
T27 2267 2193 0 0