Group : tb.dut.u_edn_cov_if::edn_error_cg
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Group : tb.dut.u_edn_cov_if::edn_error_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
75.00 75.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_error_cg 75.00 1 100 1 64 64




Group Instance : edn_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
75.00 1 100 1 64 64




Summary for Group Instance edn_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 2 6 75.00


Variables for Group Instance edn_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error_test 8 2 6 75.00 100 1 1 0


Summary for Variable cp_error_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 2 6 75.00


Automatically Generated Bins for cp_error_test

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[EdnFifoWriteErrTest] 0 1 1
auto[EdnFifoReadErrTest] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[EdnSfifoRescmdErrTest] 22 1 T16 1 T18 6 T19 5
auto[EdnSfifoGencmdErrTest] 31 1 T16 6 T18 5 T19 2
auto[EdnAckSmErrTest] 880 1 T5 1 T16 130 T31 1
auto[EdnMainSmErrTest] 880 1 T5 1 T16 130 T31 1
auto[EdnCntrErrTest] 96 1 T5 1 T16 10 T17 1
auto[EdnFifoStateErrTest] 53 1 T16 7 T18 11 T19 7

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