Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156962	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

332449

1

T1

4

T2

73

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	206635	1			T1	2		T2	33		T3	21
values[0x0]	133244	1			T2	32		T3	7		T7	15
values[0x1]	149532	1			T1	3		T2	48		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	105063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

384348

1

T1

4

T2

83

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1435	1			T16	3		T31	1		T58	1
valid_sources[0x01]	1600	1			T6	1		T30	2		T43	2
valid_sources[0x02]	1508	1			T6	2		T16	1		T28	1
valid_sources[0x03]	1523	1			T4	1		T6	7		T16	1
valid_sources[0x04]	1294	1			T6	4		T16	4		T30	7
valid_sources[0x05]	1846	1			T16	3		T30	2		T58	1
valid_sources[0x06]	1906	1			T64	1		T61	5		T62	1
valid_sources[0x07]	1554	1			T4	2		T6	1		T16	1
valid_sources[0x08]	1721	1			T16	1		T11	3		T72	1
valid_sources[0x09]	1656	1			T6	4		T16	4		T30	6
valid_sources[0x0a]	1817	1			T6	2		T16	1		T30	3
valid_sources[0x0b]	1517	1			T6	1		T30	2		T72	1
valid_sources[0x0c]	1624	1			T6	3		T43	1		T45	1
valid_sources[0x0d]	1787	1			T24	22		T38	2		T27	1
valid_sources[0x0e]	2473	1			T6	3		T72	1		T76	12
valid_sources[0x0f]	1533	1			T6	2		T30	5		T72	1
valid_sources[0x10]	1751	1			T7	2		T6	3		T16	4
valid_sources[0x11]	1940	1			T6	2		T16	3		T30	4
valid_sources[0x12]	2134	1			T6	3		T16	2		T30	1
valid_sources[0x13]	1936	1			T24	2		T6	1		T16	1
valid_sources[0x14]	1883	1			T4	1		T6	1		T16	4
valid_sources[0x15]	1837	1			T6	3		T26	2		T58	1
valid_sources[0x16]	2071	1			T7	2		T6	2		T16	1
valid_sources[0x17]	1840	1			T16	5		T74	4		T43	4
valid_sources[0x18]	2340	1			T6	3		T16	1		T30	4
valid_sources[0x19]	1680	1			T16	2		T30	2		T43	2
valid_sources[0x1a]	2133	1			T16	2		T11	1		T75	2
valid_sources[0x1b]	1942	1			T7	1		T5	3		T6	4
valid_sources[0x1c]	1439	1			T4	2		T6	1		T16	3
valid_sources[0x1d]	2171	1			T27	2		T43	1		T324	3
valid_sources[0x1e]	1701	1			T30	1		T43	1		T76	1
valid_sources[0x1f]	1817	1			T4	2		T6	1		T16	2
valid_sources[0x20]	2038	1			T6	3		T16	3		T27	1
valid_sources[0x21]	1856	1			T6	1		T16	2		T30	2
valid_sources[0x22]	1699	1			T16	2		T72	1		T28	4
valid_sources[0x23]	1746	1			T4	1		T6	1		T16	2
valid_sources[0x24]	1796	1			T16	4		T38	3		T30	5
valid_sources[0x25]	2708	1			T7	2		T6	2		T11	5
valid_sources[0x26]	2074	1			T6	3		T11	1		T38	1
valid_sources[0x27]	1543	1			T24	3		T6	1		T16	4
valid_sources[0x28]	1687	1			T30	2		T43	4		T324	2
valid_sources[0x29]	1981	1			T6	3		T16	1		T30	2
valid_sources[0x2a]	1783	1			T6	1		T16	4		T75	1
valid_sources[0x2b]	1939	1			T16	5		T30	1		T8	1
valid_sources[0x2c]	2002	1			T2	19		T16	1		T76	1
valid_sources[0x2d]	1805	1			T2	3		T16	4		T27	1
valid_sources[0x2e]	1941	1			T6	4		T16	1		T38	1
valid_sources[0x2f]	1876	1			T6	3		T38	3		T31	1
valid_sources[0x30]	1637	1			T27	1		T63	2		T43	6
valid_sources[0x31]	1774	1			T4	1		T6	2		T75	1
valid_sources[0x32]	1631	1			T7	2		T6	2		T16	2
valid_sources[0x33]	2504	1			T4	3		T16	4		T38	1
valid_sources[0x34]	1809	1			T6	4		T16	1		T26	3
valid_sources[0x35]	1647	1			T16	2		T30	1		T27	1
valid_sources[0x36]	1470	1			T6	2		T30	5		T12	114
valid_sources[0x37]	2132	1			T7	1		T4	2		T6	1
valid_sources[0x38]	2160	1			T7	3		T16	1		T30	1
valid_sources[0x39]	1706	1			T7	2		T6	1		T16	1
valid_sources[0x3a]	1788	1			T6	2		T16	1		T11	4
valid_sources[0x3b]	2249	1			T6	2		T16	4		T74	2
valid_sources[0x3c]	1685	1			T16	2		T72	1		T63	1
valid_sources[0x3d]	1590	1			T7	1		T4	1		T6	3
valid_sources[0x3e]	1837	1			T7	1		T6	1		T16	2
valid_sources[0x3f]	2049	1			T4	2		T6	1		T16	2
valid_sources[0x40]	1634	1			T28	1		T220	1		T112	2
valid_sources[0x41]	1870	1			T6	2		T16	1		T18	1
valid_sources[0x42]	1975	1			T7	3		T6	2		T16	1
valid_sources[0x43]	1951	1			T6	1		T16	3		T71	1
valid_sources[0x44]	2453	1			T6	1		T16	2		T30	5
valid_sources[0x45]	1854	1			T4	2		T6	4		T18	2
valid_sources[0x46]	2632	1			T6	1		T16	3		T75	1
valid_sources[0x47]	1500	1			T7	5		T6	3		T16	3
valid_sources[0x48]	1802	1			T7	1		T6	3		T16	2
valid_sources[0x49]	2493	1			T2	9		T16	2		T58	1
valid_sources[0x4a]	2358	1			T6	3		T30	1		T220	1
valid_sources[0x4b]	1434	1			T7	2		T6	2		T16	1
valid_sources[0x4c]	1736	1			T4	2		T6	3		T16	3
valid_sources[0x4d]	1596	1			T6	3		T268	1		T51	8
valid_sources[0x4e]	2402	1			T6	3		T30	1		T268	1
valid_sources[0x4f]	1888	1			T6	2		T16	5		T31	1
valid_sources[0x50]	1758	1			T16	3		T11	1		T30	1
valid_sources[0x51]	2149	1			T6	6		T52	1		T113	2
valid_sources[0x52]	1681	1			T6	2		T16	1		T38	1
valid_sources[0x53]	1722	1			T16	2		T27	1		T43	7
valid_sources[0x54]	1971	1			T1	5		T7	5		T16	2
valid_sources[0x55]	1874	1			T6	3		T27	2		T72	1
valid_sources[0x56]	1674	1			T6	2		T16	2		T27	1
valid_sources[0x57]	1653	1			T7	2		T6	1		T16	5
valid_sources[0x58]	1690	1			T16	2		T72	1		T43	5
valid_sources[0x59]	1969	1			T6	6		T16	1		T30	1
valid_sources[0x5a]	2368	1			T6	2		T16	1		T11	2
valid_sources[0x5b]	1770	1			T16	3		T70	1		T113	1
valid_sources[0x5c]	1677	1			T7	3		T6	2		T16	2
valid_sources[0x5d]	1783	1			T2	1		T4	4		T16	3
valid_sources[0x5e]	1570	1			T16	3		T11	1		T43	1
valid_sources[0x5f]	1380	1			T6	1		T16	2		T30	1
valid_sources[0x60]	2150	1			T24	23		T16	3		T30	2
valid_sources[0x61]	2689	1			T6	1		T58	1		T70	1
valid_sources[0x62]	2118	1			T6	1		T16	2		T26	2
valid_sources[0x63]	1425	1			T6	3		T16	4		T38	1
valid_sources[0x64]	2112	1			T7	1		T6	3		T16	3
valid_sources[0x65]	1595	1			T6	1		T16	1		T73	1
valid_sources[0x66]	2139	1			T6	3		T16	2		T58	1
valid_sources[0x67]	2006	1			T7	1		T16	3		T38	1
valid_sources[0x68]	2158	1			T6	3		T30	4		T27	1
valid_sources[0x69]	2055	1			T7	3		T4	1		T6	5
valid_sources[0x6a]	1624	1			T6	1		T16	1		T61	4
valid_sources[0x6b]	2033	1			T7	2		T6	2		T38	1
valid_sources[0x6c]	1619	1			T16	1		T38	1		T75	1
valid_sources[0x6d]	2303	1			T5	1		T6	3		T16	2
valid_sources[0x6e]	1429	1			T6	2		T16	2		T27	1
valid_sources[0x6f]	1514	1			T16	7		T30	3		T43	2
valid_sources[0x70]	2699	1			T7	1		T6	2		T16	3
valid_sources[0x71]	1504	1			T5	1		T6	3		T16	1
valid_sources[0x72]	1610	1			T6	2		T16	1		T43	2
valid_sources[0x73]	2179	1			T6	3		T16	2		T69	3
valid_sources[0x74]	1553	1			T6	2		T16	1		T11	1
valid_sources[0x75]	2362	1			T4	2		T6	1		T16	2
valid_sources[0x76]	2568	1			T7	3		T16	2		T26	1
valid_sources[0x77]	1901	1			T2	11		T11	2		T27	1
valid_sources[0x78]	2349	1			T6	1		T16	1		T30	3
valid_sources[0x79]	1404	1			T6	4		T16	2		T11	1
valid_sources[0x7a]	2170	1			T6	3		T16	2		T31	1
valid_sources[0x7b]	2059	1			T6	2		T16	4		T30	5
valid_sources[0x7c]	1591	1			T7	1		T4	1		T6	3
valid_sources[0x7d]	1858	1			T2	16		T6	1		T16	2
valid_sources[0x7e]	2477	1			T7	9		T6	3		T25	10
valid_sources[0x7f]	2134	1			T5	1		T6	4		T16	1
valid_sources[0x80]	1798	1			T7	3		T6	3		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89645

1

T1

1

T2

2

T3

4

values[0x0]

all_enables

biggest_size

122401

1

T2

28

T3

5

T7

12

values[0x1]

all_enables

biggest_size

120403

1

T1

3

T2

43

T7

13