Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1839	1			T2	3		T7	2		T6	7
non_zero_bins[1]	1242	1			T2	1		T7	1		T6	3
zero	6203	1			T1	2		T3	3		T7	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	341	1			T6	1		T30	1		T61	2
uni	2255	1			T3	1		T7	2		T24	1
gen	3083	1			T1	1		T3	1		T7	1
res	627	1			T2	2		T6	1		T11	3
ins	2978	1			T1	1		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5916

1

T1

1

T2

1

T3

3

mubi_true

3368

1

T1

1

T2

3

T7

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

33

1

T100

1

T126

1

T93

1

pass

9251

1

T1

2

T2

4

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	67	1			T30	1		T80	1		T39	2
upd	non_zero_bins[0]	pass	mubi_true	89	1			T61	2		T120	1		T116	1
upd	non_zero_bins[1]	pass	mubi_false	59	1			T6	1		T112	1		T39	1
upd	non_zero_bins[1]	pass	mubi_true	57	1			T122	2		T249	1		T253	1
upd	zero	pass	mubi_false	32	1			T310	1		T228	1		T311	1
upd	zero	pass	mubi_true	37	1			T112	1		T125	1		T53	1
uni	zero	pass	mubi_false	1725	1			T3	1		T7	1		T24	1
uni	zero	pass	mubi_true	530	1			T7	1		T6	2		T27	1
gen	non_zero_bins[0]	pass	mubi_false	377	1			T7	1		T6	1		T11	3
gen	non_zero_bins[0]	pass	mubi_true	335	1			T6	2		T51	1		T112	1
gen	non_zero_bins[1]	pass	mubi_false	199	1			T61	1		T112	1		T21	1
gen	non_zero_bins[1]	pass	mubi_true	255	1			T6	1		T22	3		T120	1
gen	zero	fail	mubi_false	30	1			T100	1		T93	1		T137	1
gen	zero	pass	mubi_false	1202	1			T3	1		T4	1		T24	1
gen	zero	pass	mubi_true	685	1			T1	1		T5	1		T24	2
res	non_zero_bins[0]	pass	mubi_false	167	1			T6	1		T45	1		T62	1
res	non_zero_bins[0]	pass	mubi_true	137	1			T2	2		T20	5		T62	1
res	non_zero_bins[1]	pass	mubi_false	78	1			T11	3		T12	2		T13	2
res	non_zero_bins[1]	pass	mubi_true	95	1			T47	2		T125	1		T39	1
res	zero	fail	mubi_false	3	1			T126	1		T176	1		T177	1
res	zero	pass	mubi_false	85	1			T21	2		T22	5		T107	1
res	zero	pass	mubi_true	62	1			T141	2		T250	1		T150	2
ins	non_zero_bins[0]	pass	mubi_false	328	1			T2	1		T6	2		T11	1
ins	non_zero_bins[0]	pass	mubi_true	339	1			T7	1		T6	1		T30	1
ins	non_zero_bins[1]	pass	mubi_false	238	1			T20	1		T43	1		T113	1
ins	non_zero_bins[1]	pass	mubi_true	261	1			T2	1		T7	1		T6	1
ins	zero	pass	mubi_false	1326	1			T1	1		T3	1		T4	1
ins	zero	pass	mubi_true	486	1			T5	2		T24	1		T6	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded