Unified Coverage Report :: Group :: csrng_agent_pkg::device_genbits_cg

Group : csrng_agent_pkg::device_genbits_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
78.57	78.57	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg	78.57	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_genbits_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	3	5	62.50

Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_glen	4	0	4	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_genbits_cross	8	3	5	62.50	100	1	1	0

Summary for Variable csrng_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_glen

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	1901	1			T1	1		T3	1		T4	1
glens[1]	44	1			T21	1		T13	1		T312	1
glens[2]	50	1			T45	1		T46	1		T59	1
glens[3]	42	1			T7	1		T14	1		T313	1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

30

1

T100

1

T93

1

T137

1

pass

3053

1

T1

1

T3

1

T7

1

---

Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	3	5	62.50	3

Automatically Generated Cross Bins for csrng_genbits_cross

Uncovered bins

csrng_glen	csrng_sts	COUNT	AT LEAST	NUMBER	STATUS
[glens[1] , glens[2] , glens[3]]	[fail]	--	--	3

Covered bins

csrng_glen	csrng_sts	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
glens[0]	fail	30	1			T100	1		T93	1		T137	1
glens[0]	pass	1871	1			T1	1		T3	1		T4	1
glens[1]	pass	44	1			T21	1		T13	1		T312	1
glens[2]	pass	50	1			T45	1		T46	1		T59	1
glens[3]	pass	42	1			T7	1		T14	1		T313	1