Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T2 T3 T7 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T2 T3 T7 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T2 T3 T7 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T2 T3 T7 
80         1/1                    state_d = AckPls;
           Tests:       T2 T3 T7 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T2 T3 T7 
85         1/1                  state_d = Idle;
           Tests:       T2 T3 T7 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T7
DataWait	75	Covered	T2,T3,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T208,T209,T221
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T7
DataWait->AckPls	80	Covered	T2,T3,T7
DataWait->Disabled	107	Covered	T2,T54,T55
DataWait->Error	99	Covered	T66,T110,T159
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T7
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T7
Idle	-	1	0	-	Covered	T2,T3,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T7
DataWait	-	-	-	0	Covered	T2,T3,T7
AckPls	-	-	-	-	Covered	T2,T3,T7
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T72,T8

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	84418516	960423	0	0
FpvSecCmErrorStEscalate_A	84418516	966800	0	0
u_state_regs_A	84385753	83219385	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84418516	960423	0	0
T5	9765	5565	0	0
T6	134379	0	0	0
T8	0	2099	0	0
T11	18823	0	0	0
T16	170128	63553	0	0
T17	0	7707	0	0
T24	17185	0	0	0
T25	9576	0	0	0
T26	8659	0	0	0
T31	20629	7910	0	0
T38	7091	0	0	0
T58	0	7882	0	0
T60	8008	0	0	0
T63	0	2436	0	0
T64	0	7966	0	0
T72	0	2316	0	0
T220	0	7476	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84418516	966800	0	0
T5	9765	5572	0	0
T6	134379	0	0	0
T8	0	2106	0	0
T11	18823	0	0	0
T16	170128	64463	0	0
T17	0	7714	0	0
T24	17185	0	0	0
T25	9576	0	0	0
T26	8659	0	0	0
T31	20629	7917	0	0
T38	7091	0	0	0
T58	0	7889	0	0
T60	8008	0	0	0
T63	0	2443	0	0
T64	0	7973	0	0
T72	0	2323	0	0
T220	0	7483	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84385753	83219385	0	0
T1	8743	8351	0	0
T2	36701	36134	0	0
T3	11487	11046	0	0
T4	13356	12516	0	0
T5	9587	8593	0	0
T6	134379	129906	0	0
T7	13468	13083	0	0
T16	170128	94864	0	0
T24	17185	16625	0	0
T25	9576	9058	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T30 T20 T52 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T30 T20 T52 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T30 T20 T52 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T30 T20 T52 
80         1/1                    state_d = AckPls;
           Tests:       T30 T20 T52 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T30 T20 T52 
85         1/1                  state_d = Idle;
           Tests:       T30 T20 T52 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T30,T20,T52
DataWait	75	Covered	T30,T20,T52
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T30,T20,T52
DataWait->AckPls	80	Covered	T30,T20,T52
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T222,T218,T167
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T30,T20,T52
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T20,T52
Idle	-	1	0	-	Covered	T30,T20,T52
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T20,T52
DataWait	-	-	-	0	Covered	T30,T52,T51
AckPls	-	-	-	-	Covered	T30,T20,T52
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T18,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	137539	0	0
FpvSecCmErrorStEscalate_A	12059788	138450	0	0
u_state_regs_A	12059788	11893164	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	137539	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	307	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	338	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	138450	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	308	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	339	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	11893164	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1910	1790	0	0
T5	1395	1253	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T7 T30 T47 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T7 T30 T47 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T7 T30 T47 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T7 T30 T47 
80         1/1                    state_d = AckPls;
           Tests:       T7 T30 T47 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T7 T30 T47 
85         1/1                  state_d = Idle;
           Tests:       T7 T30 T47 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T30,T47
DataWait	75	Covered	T7,T30,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T30,T47
DataWait->AckPls	80	Covered	T7,T30,T47
DataWait->Disabled	107	Covered	T48,T84,T168
DataWait->Error	99	Covered	T223,T212,T224
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T30,T47
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T30,T47
Idle	-	1	0	-	Covered	T7,T30,T47
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T30,T47
DataWait	-	-	-	0	Covered	T7,T30,T47
AckPls	-	-	-	-	Covered	T7,T30,T47
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T18,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	137539	0	0
FpvSecCmErrorStEscalate_A	12059788	138450	0	0
u_state_regs_A	12059788	11893164	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	137539	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	307	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	338	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	138450	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	308	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	339	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	11893164	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1910	1790	0	0
T5	1395	1253	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T26 T31 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T26 T30 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T26 T31 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T26 T31 
80         1/1                    state_d = AckPls;
           Tests:       T1 T26 T30 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T26 T30 
85         1/1                  state_d = Idle;
           Tests:       T1 T26 T30 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T26,T30
DataWait	75	Covered	T1,T26,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T26,T30
DataWait->AckPls	80	Covered	T1,T26,T30
DataWait->Disabled	107	Covered	T225,T226
DataWait->Error	99	Covered	T31,T188,T213
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T26,T31
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T58,T72

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T26,T30
Idle	-	1	0	-	Covered	T1,T26,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T26,T30
DataWait	-	-	-	0	Covered	T1,T26,T31
AckPls	-	-	-	-	Covered	T1,T26,T30
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T18,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	137539	0	0
FpvSecCmErrorStEscalate_A	12059788	138450	0	0
u_state_regs_A	12059788	11893164	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	137539	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	307	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	338	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	138450	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	308	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	339	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	11893164	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1910	1790	0	0
T5	1395	1253	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T2 T3 T7 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T2 T3 T7 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T2 T3 T7 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T2 T3 T7 
80         1/1                    state_d = AckPls;
           Tests:       T2 T3 T7 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T2 T3 T7 
85         1/1                  state_d = Idle;
           Tests:       T2 T3 T7 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T7
DataWait	75	Covered	T2,T3,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T227
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T7
DataWait->AckPls	80	Covered	T2,T3,T7
DataWait->Disabled	107	Covered	T39,T142,T228
DataWait->Error	99	Covered	T66,T159,T229
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T7
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T7
Idle	-	1	0	-	Covered	T2,T3,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T7
DataWait	-	-	-	0	Covered	T3,T7,T24
AckPls	-	-	-	-	Covered	T2,T3,T7
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T72,T8

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	135189	0	0
FpvSecCmErrorStEscalate_A	12059788	136100	0	0
u_state_regs_A	12027025	11860401	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	135189	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	257	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	288	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	136100	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	258	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	289	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12027025	11860401	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1896	1776	0	0
T5	1217	1075	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T2 T7 T30 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T2 T7 T30 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T2 T7 T30 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T2 T7 T30 
80         1/1                    state_d = AckPls;
           Tests:       T2 T7 T30 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T2 T7 T30 
85         1/1                  state_d = Idle;
           Tests:       T2 T7 T30 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T7,T30
DataWait	75	Covered	T2,T7,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T230,T231
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T7,T30
DataWait->AckPls	80	Covered	T2,T7,T30
DataWait->Disabled	107	Covered	T2,T193,T141
DataWait->Error	99	Covered	T110,T232,T129
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T7,T30
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T7,T30
Idle	-	1	0	-	Covered	T2,T7,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T7,T30
DataWait	-	-	-	0	Covered	T2,T7,T30
AckPls	-	-	-	-	Covered	T2,T7,T30
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T18,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	137539	0	0
FpvSecCmErrorStEscalate_A	12059788	138450	0	0
u_state_regs_A	12059788	11893164	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	137539	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	307	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	338	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	138450	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	308	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	339	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	11893164	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1910	1790	0	0
T5	1395	1253	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T4 T42 T51 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T4 T42 T51 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T4 T42 T51 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T4 T42 T51 
80         1/1                    state_d = AckPls;
           Tests:       T4 T42 T51 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T4 T42 T51 
85         1/1                  state_d = Idle;
           Tests:       T4 T42 T51 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T4,T42,T51
DataWait	75	Covered	T4,T42,T51
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T208,T221
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T4,T42,T51
DataWait->AckPls	80	Covered	T4,T42,T51
DataWait->Disabled	107	Covered	T54,T55,T143
DataWait->Error	99	Covered	T140,T233,T234
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T4,T42,T51
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T4,T42,T51
Idle	-	1	0	-	Covered	T4,T42,T51
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T4,T42,T51
DataWait	-	-	-	0	Covered	T42,T51,T54
AckPls	-	-	-	-	Covered	T4,T42,T51
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T18,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	137539	0	0
FpvSecCmErrorStEscalate_A	12059788	138450	0	0
u_state_regs_A	12059788	11893164	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	137539	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	307	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	338	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	138450	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	308	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	339	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	11893164	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1910	1790	0	0
T5	1395	1253	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T30 T51 T56 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T30 T51 T56 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T30 T51 T56 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T30 T51 T56 
80         1/1                    state_d = AckPls;
           Tests:       T30 T51 T56 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T30 T51 T56 
85         1/1                  state_d = Idle;
           Tests:       T30 T51 T56 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T31 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T31 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T31 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T31 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T31 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T2 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T2 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T2 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T2 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T30,T51,T56
DataWait	75	Covered	T30,T51,T56
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T31
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T209
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T30,T51,T56
DataWait->AckPls	80	Covered	T30,T51,T56
DataWait->Disabled	107	Covered	T56,T95,T235
DataWait->Error	99	Covered	T182,T130,T219
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T6,T42,T112
EndPointClear->Error	99	Covered	T5,T16,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T30,T51,T56
Idle->Disabled	107	Covered	T2,T4,T5
Idle->Error	99	Covered	T16,T31,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T51,T56
Idle	-	1	0	-	Covered	T30,T51,T56
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T51,T56
DataWait	-	-	-	0	Covered	T30,T51,T56
AckPls	-	-	-	-	Covered	T30,T51,T56
Error	-	-	-	-	Covered	T5,T16,T31
default	-	-	-	-	Covered	T16,T18,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T31
0	1	Covered	T2,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12059788	137539	0	0
FpvSecCmErrorStEscalate_A	12059788	138450	0	0
u_state_regs_A	12059788	11893164	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	137539	0	0
T5	1395	795	0	0
T6	19197	0	0	0
T8	0	307	0	0
T11	2689	0	0	0
T16	24304	9079	0	0
T17	0	1101	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1130	0	0
T38	1013	0	0	0
T58	0	1126	0	0
T60	1144	0	0	0
T63	0	348	0	0
T64	0	1138	0	0
T72	0	338	0	0
T220	0	1068	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	138450	0	0
T5	1395	796	0	0
T6	19197	0	0	0
T8	0	308	0	0
T11	2689	0	0	0
T16	24304	9209	0	0
T17	0	1102	0	0
T24	2455	0	0	0
T25	1368	0	0	0
T26	1237	0	0	0
T31	2947	1131	0	0
T38	1013	0	0	0
T58	0	1127	0	0
T60	1144	0	0	0
T63	0	349	0	0
T64	0	1139	0	0
T72	0	339	0	0
T220	0	1069	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12059788	11893164	0	0
T1	1249	1193	0	0
T2	5243	5162	0	0
T3	1641	1578	0	0
T4	1910	1790	0	0
T5	1395	1253	0	0
T6	19197	18558	0	0
T7	1924	1869	0	0
T16	24304	13552	0	0
T24	2455	2375	0	0
T25	1368	1294	0	0