Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	136	1			T3	1		T22	1		T62	1
auto_req_mode	130	1			T9	1		T49	1		T17	1
sw_mode	2018	1			T1	1		T2	1		T25	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

307

1

T3

1

T22

1

T9

1

single

93

1

T40

1

T123

1

T307

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	761	1			T1	1		T3	1		T22	1
auto[2]	88	1			T105	9		T228	61		T329	2
auto[3]	272	1			T237	72		T330	50		T331	4
auto[4]	34	1			T2	1		T27	1		T332	9
auto[5]	140	1			T322	1		T101	15		T333	6
auto[6]	27	1			T104	14		T334	1		T335	1
auto[7]	962	1			T6	9		T26	1		T39	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	88	1			T3	1		T22	1		T62	1
auto[1]	auto_req_mode	91	1			T9	1		T49	1		T17	1
auto[1]	sw_mode	582	1			T1	1		T25	1		T57	3
auto[2]	boot_req_mode	5	1			T263	1		T336	1		T337	1
auto[2]	auto_req_mode	4	1			T338	1		T339	1		T340	1
auto[2]	sw_mode	79	1			T105	9		T228	61		T329	2
auto[3]	boot_req_mode	3	1			T341	1		T342	1		T343	1
auto[3]	auto_req_mode	3	1			T344	1		T345	1		T346	1
auto[3]	sw_mode	266	1			T237	72		T330	50		T331	4
auto[4]	boot_req_mode	2	1			T310	1		T347	1		-	-
auto[4]	auto_req_mode	3	1			T348	1		T349	1		T350	1
auto[4]	sw_mode	29	1			T2	1		T27	1		T332	9
auto[5]	boot_req_mode	2	1			T351	1		T352	1		-	-
auto[5]	auto_req_mode	3	1			T353	1		T354	1		T355	1
auto[5]	sw_mode	135	1			T322	1		T101	15		T333	6
auto[6]	boot_req_mode	6	1			T335	1		T356	1		T357	1
auto[6]	auto_req_mode	2	1			T334	1		T358	1		-	-
auto[6]	sw_mode	19	1			T104	14		T359	1		T360	1
auto[7]	boot_req_mode	30	1			T123	1		T46	1		T86	1
auto[7]	auto_req_mode	24	1			T11	1		T12	1		T55	1
auto[7]	sw_mode	908	1			T6	9		T26	1		T39	1