Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cs_cmd_response_cg

Group : tb.dut.u_edn_cov_if::edn_cs_cmd_response_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cs_cmd_response_cg	100.00	1	100	1	64	64

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Group Instance : edn_cs_cmd_response_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

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Summary for Group Instance edn_cs_cmd_response_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00

Variables for Group Instance edn_cs_cmd_response_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csrng_rsp_sts_cg	5	0	5	100.00	100	1	1	0

Summary for Variable cp_csrng_rsp_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_csrng_rsp_sts_cg

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CMD_STS_UNDRIVEN]	0	Excluded
undriven	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CMD_STS_SUCCESS]	7721	1			T1	3		T2	3		T3	8
auto[CMD_STS_INVALID_ACMD]	56	1			T56	1		T44	1		T116	1
auto[CMD_STS_INVALID_GEN_CMD]	46	1			T10	1		T28	1		T115	1
auto[CMD_STS_INVALID_CMD_SEQ]	44	1			T23	1		T114	1		T88	1
auto[CMD_STS_RESEED_CNT_EXCEEDED]	54	1			T125	1		T90	1		T113	1