Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

309087

1

T1

8

T2

11

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	200581	1			T1	34		T2	54		T3	58
values[0x0]	124784	1			T1	3		T2	3		T3	13
values[0x1]	137958	1			T1	4		T2	6		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	103540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

359783

1

T1

21

T2

25

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1980	1			T6	2		T57	1		T66	3
valid_sources[0x01]	2451	1			T4	2		T6	2		T57	1
valid_sources[0x02]	1827	1			T6	4		T57	1		T14	1
valid_sources[0x03]	1392	1			T5	12		T6	7		T57	1
valid_sources[0x04]	1491	1			T6	5		T10	1		T14	1
valid_sources[0x05]	1743	1			T6	3		T57	3		T14	7
valid_sources[0x06]	2235	1			T6	3		T14	3		T66	4
valid_sources[0x07]	1658	1			T9	2		T57	1		T14	4
valid_sources[0x08]	1805	1			T6	1		T14	3		T66	1
valid_sources[0x09]	1268	1			T9	1		T6	9		T57	3
valid_sources[0x0a]	1200	1			T9	1		T57	1		T14	2
valid_sources[0x0b]	1812	1			T1	2		T25	1		T6	1
valid_sources[0x0c]	1634	1			T9	1		T14	3		T66	2
valid_sources[0x0d]	1942	1			T25	1		T6	2		T57	2
valid_sources[0x0e]	1458	1			T9	2		T25	1		T10	1
valid_sources[0x0f]	1272	1			T57	1		T14	3		T58	1
valid_sources[0x10]	1481	1			T6	1		T57	1		T14	3
valid_sources[0x11]	1713	1			T6	6		T49	2		T28	1
valid_sources[0x12]	1808	1			T6	2		T27	1		T66	1
valid_sources[0x13]	2093	1			T57	2		T10	1		T27	3
valid_sources[0x14]	2113	1			T1	1		T6	2		T57	1
valid_sources[0x15]	1376	1			T6	1		T14	5		T66	1
valid_sources[0x16]	1644	1			T14	1		T250	3		T54	1
valid_sources[0x17]	1656	1			T6	3		T14	2		T68	2
valid_sources[0x18]	1625	1			T6	2		T57	1		T14	1
valid_sources[0x19]	2035	1			T25	1		T6	3		T10	1
valid_sources[0x1a]	2113	1			T6	6		T10	1		T14	1
valid_sources[0x1b]	1817	1			T1	1		T6	4		T27	12
valid_sources[0x1c]	1355	1			T57	2		T14	3		T66	4
valid_sources[0x1d]	2206	1			T5	13		T6	2		T14	1
valid_sources[0x1e]	1927	1			T6	2		T57	1		T7	2
valid_sources[0x1f]	1248	1			T14	1		T28	1		T66	2
valid_sources[0x20]	1996	1			T6	2		T57	4		T66	2
valid_sources[0x21]	1505	1			T6	1		T14	2		T17	1
valid_sources[0x22]	1530	1			T1	1		T9	1		T25	1
valid_sources[0x23]	1751	1			T9	4		T6	5		T14	4
valid_sources[0x24]	3290	1			T4	1		T57	2		T66	1
valid_sources[0x25]	1265	1			T6	5		T14	2		T66	1
valid_sources[0x26]	1904	1			T6	12		T62	1		T49	11
valid_sources[0x27]	1950	1			T5	9		T9	1		T25	1
valid_sources[0x28]	1216	1			T6	4		T57	3		T14	6
valid_sources[0x29]	1471	1			T1	1		T9	1		T6	3
valid_sources[0x2a]	1931	1			T57	2		T66	3		T68	5
valid_sources[0x2b]	1890	1			T1	1		T9	1		T6	7
valid_sources[0x2c]	1322	1			T6	1		T57	2		T66	1
valid_sources[0x2d]	1430	1			T6	1		T57	1		T14	1
valid_sources[0x2e]	1488	1			T25	1		T14	5		T28	13
valid_sources[0x2f]	1515	1			T9	1		T6	6		T14	3
valid_sources[0x30]	1718	1			T14	3		T66	2		T59	7
valid_sources[0x31]	1971	1			T63	6		T28	1		T58	2
valid_sources[0x32]	1630	1			T17	1		T15	16		T123	1
valid_sources[0x33]	1835	1			T57	3		T14	3		T66	1
valid_sources[0x34]	1635	1			T25	1		T10	1		T14	2
valid_sources[0x35]	1555	1			T6	4		T14	2		T66	5
valid_sources[0x36]	1907	1			T24	1		T14	1		T66	2
valid_sources[0x37]	2250	1			T9	1		T25	1		T14	2
valid_sources[0x38]	2064	1			T1	1		T62	1		T57	4
valid_sources[0x39]	2159	1			T6	4		T14	4		T66	3
valid_sources[0x3a]	1936	1			T5	5		T6	2		T57	1
valid_sources[0x3b]	1529	1			T57	1		T14	2		T17	1
valid_sources[0x3c]	2283	1			T4	3		T6	3		T57	1
valid_sources[0x3d]	1837	1			T1	1		T9	1		T25	1
valid_sources[0x3e]	1786	1			T1	1		T6	10		T14	1
valid_sources[0x3f]	1951	1			T4	1		T14	4		T66	1
valid_sources[0x40]	1703	1			T6	1		T57	1		T14	6
valid_sources[0x41]	1517	1			T25	1		T57	2		T66	2
valid_sources[0x42]	1392	1			T57	2		T14	4		T66	2
valid_sources[0x43]	2016	1			T9	1		T14	1		T66	1
valid_sources[0x44]	2961	1			T1	2		T24	1		T6	2
valid_sources[0x45]	1997	1			T6	7		T14	2		T123	1
valid_sources[0x46]	1774	1			T6	1		T57	1		T49	1
valid_sources[0x47]	2213	1			T9	1		T6	2		T57	1
valid_sources[0x48]	1583	1			T9	1		T25	1		T6	2
valid_sources[0x49]	1315	1			T23	9		T9	1		T14	6
valid_sources[0x4a]	2516	1			T6	7		T57	2		T14	5
valid_sources[0x4b]	1332	1			T9	1		T6	2		T14	3
valid_sources[0x4c]	2388	1			T25	1		T6	2		T57	2
valid_sources[0x4d]	1383	1			T1	1		T9	1		T6	2
valid_sources[0x4e]	2117	1			T57	3		T14	1		T66	4
valid_sources[0x4f]	2363	1			T4	1		T9	1		T6	2
valid_sources[0x50]	1394	1			T9	1		T10	2		T14	1
valid_sources[0x51]	1665	1			T9	1		T6	8		T57	2
valid_sources[0x52]	1674	1			T9	1		T6	1		T30	25
valid_sources[0x53]	1482	1			T4	1		T9	1		T6	5
valid_sources[0x54]	2310	1			T14	2		T49	10		T66	3
valid_sources[0x55]	1459	1			T24	1		T6	4		T14	2
valid_sources[0x56]	1852	1			T5	3		T25	1		T6	2
valid_sources[0x57]	2107	1			T1	1		T66	3		T15	23
valid_sources[0x58]	2230	1			T1	1		T22	3		T9	1
valid_sources[0x59]	2227	1			T57	3		T66	1		T17	2
valid_sources[0x5a]	2490	1			T1	1		T9	2		T10	37
valid_sources[0x5b]	1813	1			T1	3		T9	1		T14	1
valid_sources[0x5c]	2058	1			T6	5		T14	1		T17	1
valid_sources[0x5d]	1590	1			T4	1		T57	2		T66	3
valid_sources[0x5e]	1839	1			T25	1		T39	352		T57	2
valid_sources[0x5f]	1307	1			T10	1		T14	4		T66	1
valid_sources[0x60]	1430	1			T4	5		T9	1		T57	1
valid_sources[0x61]	1911	1			T25	1		T6	1		T58	5
valid_sources[0x62]	4557	1			T5	5		T6	5		T14	2
valid_sources[0x63]	1579	1			T1	1		T9	1		T6	1
valid_sources[0x64]	1782	1			T6	8		T57	2		T14	4
valid_sources[0x65]	2587	1			T5	2		T14	1		T49	2
valid_sources[0x66]	1529	1			T9	1		T6	3		T57	3
valid_sources[0x67]	2013	1			T9	2		T6	3		T57	2
valid_sources[0x68]	1821	1			T3	89		T6	2		T57	1
valid_sources[0x69]	2294	1			T9	2		T57	1		T14	1
valid_sources[0x6a]	1503	1			T9	1		T14	1		T58	1
valid_sources[0x6b]	1522	1			T6	1		T14	1		T63	1
valid_sources[0x6c]	1858	1			T6	5		T57	1		T14	1
valid_sources[0x6d]	1920	1			T4	3		T6	2		T57	3
valid_sources[0x6e]	1610	1			T6	6		T57	1		T14	1
valid_sources[0x6f]	2150	1			T57	2		T10	1		T14	3
valid_sources[0x70]	1831	1			T14	4		T66	2		T58	3
valid_sources[0x71]	1179	1			T6	2		T57	1		T14	2
valid_sources[0x72]	1529	1			T9	1		T25	1		T6	4
valid_sources[0x73]	2025	1			T9	2		T25	1		T6	1
valid_sources[0x74]	1485	1			T9	2		T57	1		T27	1
valid_sources[0x75]	1906	1			T57	1		T10	1		T66	1
valid_sources[0x76]	2034	1			T14	5		T66	1		T17	1
valid_sources[0x77]	1661	1			T4	1		T66	2		T67	8
valid_sources[0x78]	1716	1			T57	1		T14	1		T66	1
valid_sources[0x79]	2201	1			T6	4		T57	1		T14	5
valid_sources[0x7a]	1651	1			T6	3		T14	1		T66	2
valid_sources[0x7b]	1529	1			T10	1		T14	1		T66	1
valid_sources[0x7c]	2154	1			T14	1		T123	4		T58	3
valid_sources[0x7d]	1912	1			T57	1		T66	1		T15	9
valid_sources[0x7e]	1571	1			T6	1		T57	1		T14	5
valid_sources[0x7f]	1487	1			T1	1		T4	3		T25	1
valid_sources[0x80]	2672	1			T6	2		T57	2		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

83711

1

T1

5

T2

7

T3

6

values[0x0]

all_enables

biggest_size

114217

1

T1

1

T2

1

T3

11

values[0x1]

all_enables

biggest_size

111159

1

T1

2

T2

3

T3

16