Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1749	1			T3	2		T6	8		T39	1
non_zero_bins[1]	1280	1			T3	1		T9	3		T6	3
zero	6081	1			T1	3		T2	3		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	320	1			T6	3		T66	3		T58	2
uni	2182	1			T1	1		T2	1		T3	3
gen	3073	1			T1	1		T2	1		T3	2
res	611	1			T5	1		T9	3		T6	1
ins	2924	1			T1	1		T2	1		T3	3

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5810

1

T1

3

T2

3

T3

6

mubi_true

3300

1

T3

2

T23

4

T9

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

37

1

T116

1

T125

1

T74

1

pass

9073

1

T1

3

T2

3

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	80	1			T6	1		T66	1		T105	1
upd	non_zero_bins[0]	pass	mubi_true	81	1			T6	1		T58	2		T301	1
upd	non_zero_bins[1]	pass	mubi_false	46	1			T6	1		T37	1		T302	1
upd	non_zero_bins[1]	pass	mubi_true	51	1			T66	1		T53	1		T303	1
upd	zero	pass	mubi_false	35	1			T101	1		T104	1		T304	1
upd	zero	pass	mubi_true	27	1			T66	1		T226	1		T227	1
uni	zero	pass	mubi_false	1652	1			T1	1		T2	1		T3	3
uni	zero	pass	mubi_true	530	1			T6	3		T57	2		T64	1
gen	non_zero_bins[0]	pass	mubi_false	373	1			T3	1		T66	2		T102	1
gen	non_zero_bins[0]	pass	mubi_true	304	1			T68	3		T58	2		T18	4
gen	non_zero_bins[1]	pass	mubi_false	243	1			T40	1		T101	1		T105	1
gen	non_zero_bins[1]	pass	mubi_true	265	1			T6	1		T123	1		T58	2
gen	zero	fail	mubi_false	33	1			T116	1		T125	1		T74	1
gen	zero	pass	mubi_false	1189	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	666	1			T23	3		T6	3		T39	1
res	non_zero_bins[0]	pass	mubi_false	145	1			T40	1		T18	2		T101	1
res	non_zero_bins[0]	pass	mubi_true	142	1			T6	1		T49	1		T68	2
res	non_zero_bins[1]	pass	mubi_false	95	1			T102	1		T45	3		T78	4
res	non_zero_bins[1]	pass	mubi_true	104	1			T9	3		T17	3		T58	1
res	zero	fail	mubi_false	4	1			T166	1		T305	1		T306	1
res	zero	pass	mubi_false	72	1			T5	1		T7	1		T44	1
res	zero	pass	mubi_true	49	1			T307	1		T107	1		T103	1
ins	non_zero_bins[0]	pass	mubi_false	320	1			T3	1		T6	3		T17	1
ins	non_zero_bins[0]	pass	mubi_true	304	1			T6	2		T39	1		T40	1
ins	non_zero_bins[1]	pass	mubi_false	227	1			T39	1		T66	1		T68	1
ins	non_zero_bins[1]	pass	mubi_true	249	1			T3	1		T6	1		T49	1
ins	zero	pass	mubi_false	1296	1			T1	1		T2	1		T4	1
ins	zero	pass	mubi_true	528	1			T3	1		T23	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded