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Module Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_edn_cmd_req_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_edn_fatal_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_edn_cmd_req_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_edn_fatal_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_boot_ins_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_boot_gen_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_reg_rdy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_rdy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_sts


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_boot_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_boot_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_auto_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_auto_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_type.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_cmd_type


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_ack.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_cmd_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_sts.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_cmd_sts


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_max_num_reqs_between_reseeds


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_edn_enable_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_boot_req_mode_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
tb.dut.u_reg.u_regwen.wr_en_data_arb
tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_boot_mode.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_auto_mode.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_cmd_type.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_cmd_ack.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_cmd_sts.wr_en_data_arb
tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T6
10CoveredT1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T4 T5 T6  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T5,T6

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T4 T5 T6  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T5,T6

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T2 T26 T27  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T26,T27

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT2,T26,T27
10CoveredT2,T26,T27
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T26,T27
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T22 T23  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T22,T23

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T22,T23

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T22,T23
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T3 T22 T23  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT3,T22,T23

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T22,T23

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T22,T23
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_boot_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_auto_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_type.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_ack.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_sts.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T5 T9 T10  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T9,T10

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T9,T10

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T9,T10

Branch Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T5,T9,T10
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T71,T113
10CoveredT23,T10,T28

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T71,T113
11CoveredT10,T71,T113

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T71,T113

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T10,T28
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT114,T72,T74
10CoveredT23,T10,T28

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT114,T72,T74
11CoveredT114,T72,T74

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT114,T72,T74

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T10,T28
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%