Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	130	1			T22	1		T26	1		T27	1
auto_req_mode	142	1			T10	1		T9	1		T13	1
sw_mode	2047	1			T1	1		T2	1		T3	2

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

309

1

T10

1

T9

1

T22

1

single

91

1

T39

1

T43

1

T68

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	891	1			T1	1		T2	1		T3	2
auto[2]	109	1			T39	1		T130	1		T115	15
auto[3]	79	1			T26	1		T309	1		T247	6
auto[4]	63	1			T127	1		T328	12		T329	4
auto[5]	49	1			T77	1		T50	1		T330	3
auto[6]	103	1			T43	1		T70	1		T60	7
auto[7]	1025	1			T10	1		T25	1		T58	10

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	81	1			T22	1		T27	1		T40	1
auto[1]	auto_req_mode	88	1			T9	1		T13	1		T19	1
auto[1]	sw_mode	722	1			T1	1		T2	1		T3	2
auto[2]	boot_req_mode	6	1			T39	1		T310	1		T260	1
auto[2]	auto_req_mode	4	1			T11	1		T331	1		T332	1
auto[2]	sw_mode	99	1			T130	1		T115	15		T37	35
auto[3]	boot_req_mode	4	1			T26	1		T333	1		T334	1
auto[3]	auto_req_mode	3	1			T335	1		T336	1		T337	1
auto[3]	sw_mode	72	1			T309	1		T247	6		T314	1
auto[4]	boot_req_mode	5	1			T338	1		T339	1		T340	1
auto[4]	auto_req_mode	3	1			T12	1		T341	1		T342	1
auto[4]	sw_mode	55	1			T127	1		T328	12		T329	4
auto[5]	boot_req_mode	3	1			T343	1		T344	1		T345	1
auto[5]	auto_req_mode	4	1			T51	1		T346	1		T347	1
auto[5]	sw_mode	42	1			T77	1		T50	1		T330	3
auto[6]	boot_req_mode	2	1			T348	1		T349	1		-	-
auto[6]	auto_req_mode	5	1			T43	1		T350	1		T351	1
auto[6]	sw_mode	96	1			T70	1		T60	7		T118	1
auto[7]	boot_req_mode	29	1			T87	1		T91	1		T106	1
auto[7]	auto_req_mode	35	1			T10	1		T47	1		T97	1
auto[7]	sw_mode	961	1			T25	1		T58	10		T117	1