Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

299410

1

T1

10

T2

6

T3

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	191881	1			T1	23		T2	28		T3	55
values[0x0]	120232	1			T1	5		T2	4		T3	11
values[0x1]	134898	1			T1	5		T2	4		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	99697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

347314

1

T1

14

T2

16

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1565	1			T10	2		T6	1		T8	1
valid_sources[0x01]	1586	1			T10	1		T4	6		T23	1
valid_sources[0x02]	2902	1			T21	1		T28	1		T43	2
valid_sources[0x03]	2286	1			T10	2		T23	2		T6	1
valid_sources[0x04]	2287	1			T23	1		T117	1		T305	1
valid_sources[0x05]	1827	1			T8	1		T135	1		T61	1
valid_sources[0x06]	1435	1			T10	2		T30	42		T61	1
valid_sources[0x07]	1700	1			T135	2		T55	2		T43	2
valid_sources[0x08]	1940	1			T10	2		T6	1		T19	1
valid_sources[0x09]	1749	1			T10	1		T28	1		T8	1
valid_sources[0x0a]	1495	1			T10	3		T39	3		T43	4
valid_sources[0x0b]	1937	1			T10	2		T5	4		T28	1
valid_sources[0x0c]	1317	1			T10	2		T23	2		T8	2
valid_sources[0x0d]	1388	1			T10	3		T6	1		T29	1
valid_sources[0x0e]	2324	1			T10	1		T84	1		T61	1
valid_sources[0x0f]	2206	1			T10	1		T7	16		T43	2
valid_sources[0x10]	2311	1			T10	3		T4	1		T5	6
valid_sources[0x11]	1788	1			T10	1		T5	2		T28	2
valid_sources[0x12]	2236	1			T10	1		T21	2		T29	1
valid_sources[0x13]	1435	1			T135	1		T55	1		T72	1
valid_sources[0x14]	1769	1			T10	4		T24	75		T43	2
valid_sources[0x15]	1563	1			T10	3		T6	1		T61	1
valid_sources[0x16]	1576	1			T10	1		T5	6		T23	1
valid_sources[0x17]	2157	1			T10	2		T61	1		T43	1
valid_sources[0x18]	2094	1			T10	1		T6	1		T39	5
valid_sources[0x19]	1519	1			T10	2		T5	1		T43	1
valid_sources[0x1a]	1696	1			T10	1		T28	1		T29	1
valid_sources[0x1b]	1538	1			T10	2		T26	6		T61	1
valid_sources[0x1c]	1725	1			T10	1		T22	5		T135	1
valid_sources[0x1d]	1402	1			T10	1		T4	2		T39	4
valid_sources[0x1e]	1747	1			T3	85		T10	2		T6	1
valid_sources[0x1f]	1907	1			T10	1		T6	2		T60	1
valid_sources[0x20]	1814	1			T13	1		T135	1		T43	1
valid_sources[0x21]	1567	1			T10	1		T21	6		T5	1
valid_sources[0x22]	1619	1			T10	1		T5	4		T23	1
valid_sources[0x23]	1486	1			T10	1		T23	1		T79	1
valid_sources[0x24]	1914	1			T29	1		T43	4		T56	1
valid_sources[0x25]	1761	1			T10	2		T6	3		T81	1
valid_sources[0x26]	1684	1			T80	8		T117	1		T43	2
valid_sources[0x27]	1702	1			T10	1		T26	4		T7	3
valid_sources[0x28]	1828	1			T28	1		T81	1		T39	7
valid_sources[0x29]	2060	1			T10	1		T28	1		T6	2
valid_sources[0x2a]	2051	1			T8	3		T55	2		T20	1
valid_sources[0x2b]	1463	1			T23	2		T28	1		T117	1
valid_sources[0x2c]	1442	1			T10	3		T60	9		T72	3
valid_sources[0x2d]	2054	1			T10	2		T6	2		T79	1
valid_sources[0x2e]	1719	1			T21	1		T23	4		T41	1
valid_sources[0x2f]	1457	1			T10	1		T5	1		T117	1
valid_sources[0x30]	1378	1			T10	2		T28	1		T8	1
valid_sources[0x31]	1967	1			T10	2		T79	2		T8	1
valid_sources[0x32]	1711	1			T13	3		T43	1		T70	1
valid_sources[0x33]	1787	1			T10	6		T61	1		T43	1
valid_sources[0x34]	1717	1			T10	3		T29	1		T135	3
valid_sources[0x35]	1561	1			T10	3		T6	2		T40	1
valid_sources[0x36]	1963	1			T81	1		T117	2		T43	3
valid_sources[0x37]	2011	1			T39	7		T13	1		T305	4
valid_sources[0x38]	1762	1			T10	1		T23	1		T43	3
valid_sources[0x39]	1359	1			T10	1		T4	2		T9	2
valid_sources[0x3a]	1582	1			T10	1		T39	2		T43	3
valid_sources[0x3b]	1762	1			T10	1		T9	11		T43	1
valid_sources[0x3c]	1282	1			T10	1		T26	6		T6	2
valid_sources[0x3d]	1714	1			T23	1		T7	5		T13	2
valid_sources[0x3e]	1480	1			T10	1		T79	1		T13	1
valid_sources[0x3f]	1568	1			T29	1		T43	1		T72	2
valid_sources[0x40]	1680	1			T10	2		T8	1		T118	1
valid_sources[0x41]	2000	1			T10	1		T5	1		T6	1
valid_sources[0x42]	1658	1			T135	1		T42	1		T273	1
valid_sources[0x43]	1619	1			T10	1		T39	8		T135	1
valid_sources[0x44]	1425	1			T29	1		T61	1		T43	1
valid_sources[0x45]	1802	1			T29	1		T60	10		T42	1
valid_sources[0x46]	1622	1			T10	2		T26	5		T29	1
valid_sources[0x47]	1737	1			T10	2		T21	3		T117	1
valid_sources[0x48]	1752	1			T10	5		T4	1		T29	2
valid_sources[0x49]	2008	1			T10	2		T61	1		T117	1
valid_sources[0x4a]	2422	1			T10	3		T24	3		T26	2
valid_sources[0x4b]	1505	1			T10	1		T28	1		T6	3
valid_sources[0x4c]	1908	1			T6	3		T8	2		T72	3
valid_sources[0x4d]	1785	1			T13	8		T55	1		T43	1
valid_sources[0x4e]	2283	1			T135	1		T61	1		T43	3
valid_sources[0x4f]	2044	1			T27	6		T13	1		T8	1
valid_sources[0x50]	1712	1			T5	1		T9	2		T43	1
valid_sources[0x51]	1249	1			T10	1		T23	1		T55	1
valid_sources[0x52]	1552	1			T10	2		T61	1		T80	4
valid_sources[0x53]	1738	1			T10	2		T135	1		T41	1
valid_sources[0x54]	1999	1			T10	2		T43	1		T69	5
valid_sources[0x55]	1924	1			T10	1		T305	1		T72	2
valid_sources[0x56]	2642	1			T10	1		T9	14		T135	1
valid_sources[0x57]	1849	1			T10	2		T26	1		T55	1
valid_sources[0x58]	1820	1			T10	1		T6	2		T61	1
valid_sources[0x59]	1677	1			T10	3		T28	1		T29	1
valid_sources[0x5a]	1429	1			T4	1		T29	1		T16	1
valid_sources[0x5b]	1343	1			T10	4		T5	3		T135	1
valid_sources[0x5c]	1602	1			T72	1		T273	3		T20	2
valid_sources[0x5d]	1767	1			T28	1		T81	3		T8	1
valid_sources[0x5e]	2192	1			T10	1		T29	1		T7	7
valid_sources[0x5f]	1646	1			T10	2		T23	1		T29	1
valid_sources[0x60]	1745	1			T10	1		T28	1		T8	1
valid_sources[0x61]	1421	1			T10	2		T4	3		T28	1
valid_sources[0x62]	1779	1			T26	2		T8	1		T305	3
valid_sources[0x63]	2197	1			T10	3		T117	1		T41	1
valid_sources[0x64]	1926	1			T10	2		T43	3		T354	1
valid_sources[0x65]	2078	1			T81	2		T8	1		T117	1
valid_sources[0x66]	2237	1			T10	1		T26	2		T8	1
valid_sources[0x67]	1538	1			T135	1		T19	1		T80	1
valid_sources[0x68]	2475	1			T10	1		T9	14		T135	2
valid_sources[0x69]	1623	1			T10	1		T21	5		T23	1
valid_sources[0x6a]	1867	1			T10	5		T13	6		T30	3
valid_sources[0x6b]	1545	1			T10	6		T8	1		T135	1
valid_sources[0x6c]	1302	1			T10	2		T4	2		T23	1
valid_sources[0x6d]	1582	1			T10	1		T5	1		T9	6
valid_sources[0x6e]	1501	1			T39	4		T61	1		T117	1
valid_sources[0x6f]	1714	1			T23	1		T28	2		T29	1
valid_sources[0x70]	1700	1			T39	1		T13	6		T60	12
valid_sources[0x71]	2092	1			T6	1		T135	1		T43	3
valid_sources[0x72]	1554	1			T29	1		T43	2		T42	5
valid_sources[0x73]	2014	1			T10	2		T29	2		T8	1
valid_sources[0x74]	1726	1			T10	4		T9	1		T28	2
valid_sources[0x75]	2221	1			T10	3		T79	1		T43	1
valid_sources[0x76]	1562	1			T10	1		T61	1		T305	1
valid_sources[0x77]	1595	1			T61	2		T43	4		T354	1
valid_sources[0x78]	1396	1			T10	1		T5	3		T61	2
valid_sources[0x79]	2405	1			T26	5		T55	1		T60	7
valid_sources[0x7a]	1947	1			T8	1		T135	1		T117	1
valid_sources[0x7b]	1607	1			T10	2		T4	1		T29	1
valid_sources[0x7c]	1508	1			T81	6		T29	2		T60	1
valid_sources[0x7d]	1453	1			T29	1		T60	4		T17	2
valid_sources[0x7e]	1858	1			T10	2		T29	1		T43	1
valid_sources[0x7f]	1645	1			T23	1		T29	1		T7	4
valid_sources[0x80]	2129	1			T10	1		T8	1		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81104

1

T1

5

T2

1

T3

11

values[0x0]

all_enables

biggest_size

109787

1

T1

3

T2

2

T3

9

values[0x1]

all_enables

biggest_size

108519

1

T1

2

T2

3

T3

13