Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1735	1			T3	2		T10	6		T26	2
non_zero_bins[1]	1248	1			T9	2		T26	1		T39	1
zero	5962	1			T1	3		T2	3		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	281	1			T26	1		T39	1		T58	1
uni	2124	1			T1	1		T2	1		T3	2
gen	3053	1			T1	1		T2	1		T3	2
res	612	1			T3	1		T10	2		T9	2
ins	2875	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5718

1

T1

2

T2

3

T3

6

mubi_true

3227

1

T1

1

T3

1

T10

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

37

1

T55

1

T56

1

T133

1

pass

8908

1

T1

3

T2

3

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	81	1			T58	1		T60	1		T115	2
upd	non_zero_bins[0]	pass	mubi_true	53	1			T26	1		T44	1		T306	1
upd	non_zero_bins[1]	pass	mubi_false	40	1			T39	1		T247	1		T307	1
upd	non_zero_bins[1]	pass	mubi_true	41	1			T119	1		T123	1		T308	1
upd	zero	pass	mubi_false	37	1			T59	1		T126	1		T115	1
upd	zero	pass	mubi_true	29	1			T309	1		T123	1		T36	1
uni	zero	pass	mubi_false	1618	1			T2	1		T3	2		T10	1
uni	zero	pass	mubi_true	506	1			T1	1		T23	1		T81	1
gen	non_zero_bins[0]	pass	mubi_false	312	1			T10	5		T58	1		T19	3
gen	non_zero_bins[0]	pass	mubi_true	358	1			T10	1		T39	1		T135	1
gen	non_zero_bins[1]	pass	mubi_false	344	1			T58	1		T59	3		T60	1
gen	non_zero_bins[1]	pass	mubi_true	198	1			T26	1		T122	1		T123	1
gen	zero	fail	mubi_false	30	1			T55	1		T56	1		T133	1
gen	zero	pass	mubi_false	1137	1			T1	1		T2	1		T3	2
gen	zero	pass	mubi_true	674	1			T28	2		T26	1		T29	2
res	non_zero_bins[0]	pass	mubi_false	136	1			T3	1		T59	1		T115	1
res	non_zero_bins[0]	pass	mubi_true	142	1			T67	3		T74	1		T126	2
res	non_zero_bins[1]	pass	mubi_false	67	1			T42	1		T310	1		T308	1
res	non_zero_bins[1]	pass	mubi_true	112	1			T9	2		T13	1		T19	3
res	zero	fail	mubi_false	7	1			T181	1		T311	1		T312	1
res	zero	pass	mubi_false	77	1			T58	1		T43	2		T88	3
res	zero	pass	mubi_true	71	1			T10	2		T60	1		T88	1
ins	non_zero_bins[0]	pass	mubi_false	338	1			T26	1		T135	1		T58	1
ins	non_zero_bins[0]	pass	mubi_true	315	1			T3	1		T19	1		T67	1
ins	non_zero_bins[1]	pass	mubi_false	222	1			T59	1		T72	1		T42	2
ins	non_zero_bins[1]	pass	mubi_true	224	1			T135	1		T58	1		T59	1
ins	zero	pass	mubi_false	1272	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	504	1			T10	1		T22	2		T28	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded