Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T95,T220,T221
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T84,T68,T73
DataWait->Error	99	Covered	T5,T7,T120
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T5,T7

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T4,T61,T41

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	78090950	1024682	0	0
FpvSecCmErrorStEscalate_A	78090950	1031941	0	0
u_state_regs_A	78057516	76834665	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78090950	1024682	0	0
T4	9723	4458	0	0
T5	8316	2611	0	0
T6	4991	0	0	0
T7	0	2639	0	0
T8	0	4760	0	0
T9	16849	0	0	0
T14	0	7714	0	0
T15	0	4410	0	0
T21	7896	0	0	0
T22	9009	0	0	0
T23	8022	0	0	0
T24	7840	0	0	0
T26	16814	0	0	0
T28	12341	0	0	0
T41	0	4206	0	0
T61	0	7706	0	0
T69	0	4199	0	0
T120	0	2450	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78090950	1031941	0	0
T4	9723	4465	0	0
T5	8316	2618	0	0
T6	4991	0	0	0
T7	0	2646	0	0
T8	0	4767	0	0
T9	16849	0	0	0
T14	0	7721	0	0
T15	0	4417	0	0
T21	7896	0	0	0
T22	9009	0	0	0
T23	8022	0	0	0
T24	7840	0	0	0
T26	16814	0	0	0
T28	12341	0	0	0
T41	0	4213	0	0
T61	0	7713	0	0
T69	0	4206	0	0
T120	0	2457	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78057516	76834665	0	0
T1	9394	8708	0	0
T2	7490	6888	0	0
T3	20720	20111	0	0
T4	9571	8640	0	0
T5	8087	7100	0	0
T9	16849	16485	0	0
T10	23100	22638	0	0
T21	7896	7455	0	0
T22	9009	8414	0	0
T23	8022	7525	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T22 T26 T39 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T22 T26 T39 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T22 T26 T39 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T22 T26 T39 
80         1/1                    state_d = AckPls;
           Tests:       T22 T26 T39 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T22 T26 T39 
85         1/1                  state_d = Idle;
           Tests:       T22 T26 T39 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T22,T26,T39
DataWait	75	Covered	T22,T26,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T22,T26,T39
DataWait->AckPls	80	Covered	T22,T26,T39
DataWait->Disabled	107	Covered	T82,T222,T174
DataWait->Error	99	Covered	T190,T223,T137
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T22,T26,T39
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T22,T26,T39
Idle	-	1	0	-	Covered	T22,T26,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T22,T26,T39
DataWait	-	-	-	0	Covered	T22,T26,T39
AckPls	-	-	-	-	Covered	T22,T26,T39
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	146676	0	0
FpvSecCmErrorStEscalate_A	11155850	147713	0	0
u_state_regs_A	11155850	10981157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	146676	0	0
T4	1389	644	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	608	0	0
T61	0	1108	0	0
T69	0	607	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	147713	0	0
T4	1389	645	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	609	0	0
T61	0	1109	0	0
T69	0	608	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T5 T26 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T26 T29 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T5 T26 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T5 T26 
80         1/1                    state_d = AckPls;
           Tests:       T10 T26 T29 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T26 T29 
85         1/1                  state_d = Idle;
           Tests:       T10 T26 T29 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T26,T29
DataWait	75	Covered	T10,T5,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T26,T29
DataWait->AckPls	80	Covered	T10,T26,T29
DataWait->Disabled	107	Covered	T84,T73,T151
DataWait->Error	99	Covered	T5,T15,T124
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T5,T26
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T7,T61

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T26,T29
Idle	-	1	0	-	Covered	T10,T5,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T26,T29
DataWait	-	-	-	0	Covered	T10,T5,T26
AckPls	-	-	-	-	Covered	T10,T26,T29
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	146676	0	0
FpvSecCmErrorStEscalate_A	11155850	147713	0	0
u_state_regs_A	11155850	10981157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	146676	0	0
T4	1389	644	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	608	0	0
T61	0	1108	0	0
T69	0	607	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	147713	0	0
T4	1389	645	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	609	0	0
T61	0	1109	0	0
T69	0	608	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T40 T30 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T40 T30 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T40 T30 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T40 T30 
80         1/1                    state_d = AckPls;
           Tests:       T10 T40 T30 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T40 T30 
85         1/1                  state_d = Idle;
           Tests:       T10 T40 T30 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T40,T30
DataWait	75	Covered	T10,T40,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T40,T30
DataWait->AckPls	80	Covered	T10,T40,T30
DataWait->Disabled	107	Covered	T88,T152,T224
DataWait->Error	99	Covered	T57,T218,T225
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T40,T30
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T40,T30
Idle	-	1	0	-	Covered	T10,T40,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T40,T30
DataWait	-	-	-	0	Covered	T10,T40,T30
AckPls	-	-	-	-	Covered	T10,T40,T30
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	146676	0	0
FpvSecCmErrorStEscalate_A	11155850	147713	0	0
u_state_regs_A	11155850	10981157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	146676	0	0
T4	1389	644	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	608	0	0
T61	0	1108	0	0
T69	0	607	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	147713	0	0
T4	1389	645	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	609	0	0
T61	0	1109	0	0
T69	0	608	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T13 T19 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T13 T19 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T13 T19 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T13 T19 
80         1/1                    state_d = AckPls;
           Tests:       T10 T13 T19 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T13 T19 
85         1/1                  state_d = Idle;
           Tests:       T10 T13 T19 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T13,T19
DataWait	75	Covered	T10,T13,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T13,T19
DataWait->AckPls	80	Covered	T10,T13,T19
DataWait->Disabled	107	Covered	T52,T94,T226
DataWait->Error	99	Covered	T161,T150
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T13,T19
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T13,T19
Idle	-	1	0	-	Covered	T10,T13,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T13,T19
DataWait	-	-	-	0	Covered	T10,T13,T19
AckPls	-	-	-	-	Covered	T10,T13,T19
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	146676	0	0
FpvSecCmErrorStEscalate_A	11155850	147713	0	0
u_state_regs_A	11155850	10981157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	146676	0	0
T4	1389	644	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	608	0	0
T61	0	1108	0	0
T69	0	607	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	147713	0	0
T4	1389	645	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	609	0	0
T61	0	1109	0	0
T69	0	608	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T220
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T68,T227,T36
DataWait->Error	99	Covered	T7,T120,T228
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T4,T61,T41

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	144626	0	0
FpvSecCmErrorStEscalate_A	11155850	145663	0	0
u_state_regs_A	11122416	10947723	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	144626	0	0
T4	1389	594	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	558	0	0
T61	0	1058	0	0
T69	0	557	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	145663	0	0
T4	1389	595	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	559	0	0
T61	0	1059	0	0
T69	0	558	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11122416	10947723	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1237	1104	0	0
T5	959	818	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T41 T42 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T41 T42 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T41 T42 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T41 T42 
80         1/1                    state_d = AckPls;
           Tests:       T10 T41 T42 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T41 T42 
85         1/1                  state_d = Idle;
           Tests:       T10 T41 T42 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T41,T42
DataWait	75	Covered	T10,T41,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T95
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T41,T42
DataWait->AckPls	80	Covered	T10,T41,T42
DataWait->Disabled	107	Covered	T42,T229,T153
DataWait->Error	99	Covered	T189,T206,T230
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T41,T42
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T41,T42
Idle	-	1	0	-	Covered	T10,T41,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T41,T42
DataWait	-	-	-	0	Covered	T10,T42,T44
AckPls	-	-	-	-	Covered	T10,T41,T42
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	146676	0	0
FpvSecCmErrorStEscalate_A	11155850	147713	0	0
u_state_regs_A	11155850	10981157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	146676	0	0
T4	1389	644	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	608	0	0
T61	0	1108	0	0
T69	0	607	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	147713	0	0
T4	1389	645	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	609	0	0
T61	0	1109	0	0
T69	0	608	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T27 T30 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T27 T30 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T27 T30 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T27 T30 
80         1/1                    state_d = AckPls;
           Tests:       T10 T27 T30 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T27 T30 
85         1/1                  state_d = Idle;
           Tests:       T10 T27 T30 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T4 T5 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T4 T5 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T4 T5 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T4 T5 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T4 T5 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T5 T9 T22 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T5 T9 T22 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T5 T9 T22 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T5 T9 T22 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T9,T22

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T27,T30
DataWait	75	Covered	T10,T27,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T221
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T27,T30
DataWait->AckPls	80	Covered	T10,T27,T30
DataWait->Disabled	107	Covered	T27,T105,T108
DataWait->Error	99	Covered	T196,T231
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T58,T59,T60
EndPointClear->Error	99	Covered	T8,T14,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T27,T30
Idle->Disabled	107	Covered	T5,T9,T22
Idle->Error	99	Covered	T4,T5,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T27,T30
Idle	-	1	0	-	Covered	T10,T27,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T27,T30
DataWait	-	-	-	0	Covered	T10,T27,T67
AckPls	-	-	-	-	Covered	T10,T27,T30
Error	-	-	-	-	Covered	T4,T5,T7
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T5,T9,T22
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11155850	146676	0	0
FpvSecCmErrorStEscalate_A	11155850	147713	0	0
u_state_regs_A	11155850	10981157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	146676	0	0
T4	1389	644	0	0
T5	1188	373	0	0
T6	713	0	0	0
T7	0	377	0	0
T8	0	680	0	0
T9	2407	0	0	0
T14	0	1102	0	0
T15	0	630	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	608	0	0
T61	0	1108	0	0
T69	0	607	0	0
T120	0	350	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	147713	0	0
T4	1389	645	0	0
T5	1188	374	0	0
T6	713	0	0	0
T7	0	378	0	0
T8	0	681	0	0
T9	2407	0	0	0
T14	0	1103	0	0
T15	0	631	0	0
T21	1128	0	0	0
T22	1287	0	0	0
T23	1146	0	0	0
T24	1120	0	0	0
T26	2402	0	0	0
T28	1763	0	0	0
T41	0	609	0	0
T61	0	1109	0	0
T69	0	608	0	0
T120	0	351	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0