Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.16	95.00	92.31			100.00	93.33

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33

---

Module Instance : tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.16	95.00	92.31			100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.16	95.00	92.31			100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T1 T2 T3 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        1/1                  mask <= ppc_out;
           Tests:       T1 T2 T3 
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109                             data_o = '0;
110                             for (int i = 0 ; i < N ; i++) begin
111                               if (winner[i]) begin
112                                 data_o = data_i[i];
113                               end
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120        0/1     ==>        assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T1 T2 T3 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T5,T22
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T10,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==>
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	11155850	10981157	0	0
CheckNGreaterZero_A	945	945	0	0
GntImpliesReady_A	11155850	11645	0	0
GntImpliesValid_A	11155850	11645	0	0
GrantKnown_A	11155850	10981157	0	0
IdxKnown_A	11155850	10981157	0	0
IndexIsCorrect_A	11155850	11645	0	0
LockArbDecision_A	11155850	1200069	0	0
NoReadyValidNoGrant_A	11155850	9687093	0	0
ReadyAndValidImplyGrant_A	11155850	11645	0	0
ReqAndReadyImplyGrant_A	11155850	11645	0	0
ReqImpliesValid_A	11155850	1212719	0	0
ReqStaysHighUntilGranted0_M	11155850	1200069	0	0
RoundRobin_A	11155850	0	0	945
ValidKnown_A	11155850	10981157	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	945	945	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	11645	0	0
T1	1342	1	0	0
T2	1070	1	0	0
T3	2960	1	0	0
T4	1389	1	0	0
T5	1188	0	0	0
T9	2407	1	0	0
T10	3300	69	0	0
T21	1128	0	0	0
T22	1287	1	0	0
T23	1146	1	0	0
T24	0	1	0	0
T28	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	11645	0	0
T1	1342	1	0	0
T2	1070	1	0	0
T3	2960	1	0	0
T4	1389	1	0	0
T5	1188	0	0	0
T9	2407	1	0	0
T10	3300	69	0	0
T21	1128	0	0	0
T22	1287	1	0	0
T23	1146	1	0	0
T24	0	1	0	0
T28	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	11645	0	0
T1	1342	1	0	0
T2	1070	1	0	0
T3	2960	1	0	0
T4	1389	1	0	0
T5	1188	0	0	0
T9	2407	1	0	0
T10	3300	69	0	0
T21	1128	0	0	0
T22	1287	1	0	0
T23	1146	1	0	0
T24	0	1	0	0
T28	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	1200069	0	0
T1	1342	65	0	0
T2	1070	61	0	0
T3	2960	59	0	0
T4	1389	0	0	0
T5	1188	447	0	0
T9	2407	71	0	0
T10	3300	1834	0	0
T21	1128	0	0	0
T22	1287	62	0	0
T23	1146	52	0	0
T24	0	66	0	0
T28	0	46	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	9687093	0	0
T1	1342	1178	0	0
T2	1070	922	0	0
T3	2960	2813	0	0
T4	1389	1187	0	0
T5	1188	599	0	0
T9	2407	1766	0	0
T10	3300	1280	0	0
T21	1128	1065	0	0
T22	1287	158	0	0
T23	1146	1022	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	11645	0	0
T1	1342	1	0	0
T2	1070	1	0	0
T3	2960	1	0	0
T4	1389	1	0	0
T5	1188	0	0	0
T9	2407	1	0	0
T10	3300	69	0	0
T21	1128	0	0	0
T22	1287	1	0	0
T23	1146	1	0	0
T24	0	1	0	0
T28	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	11645	0	0
T1	1342	1	0	0
T2	1070	1	0	0
T3	2960	1	0	0
T4	1389	1	0	0
T5	1188	0	0	0
T9	2407	1	0	0
T10	3300	69	0	0
T21	1128	0	0	0
T22	1287	1	0	0
T23	1146	1	0	0
T24	0	1	0	0
T28	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	1212719	0	0
T1	1342	66	0	0
T2	1070	62	0	0
T3	2960	60	0	0
T4	1389	1	0	0
T5	1188	448	0	0
T9	2407	72	0	0
T10	3300	1903	0	0
T21	1128	0	0	0
T22	1287	63	0	0
T23	1146	53	0	0
T24	0	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	1200069	0	0
T1	1342	65	0	0
T2	1070	61	0	0
T3	2960	59	0	0
T4	1389	0	0	0
T5	1188	447	0	0
T9	2407	71	0	0
T10	3300	1834	0	0
T21	1128	0	0	0
T22	1287	62	0	0
T23	1146	52	0	0
T24	0	66	0	0
T28	0	46	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	0	0	945

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11155850	10981157	0	0
T1	1342	1244	0	0
T2	1070	984	0	0
T3	2960	2873	0	0
T4	1389	1256	0	0
T5	1188	1047	0	0
T9	2407	2355	0	0
T10	3300	3234	0	0
T21	1128	1065	0	0
T22	1287	1202	0	0
T23	1146	1075	0	0