Group : tb.dut.u_edn_cov_if::edn_cs_cmd_response_cg
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Group : tb.dut.u_edn_cov_if::edn_cs_cmd_response_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmd_response_cg 100.00 1 100 1 64 64




Group Instance : edn_cs_cmd_response_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cs_cmd_response_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00


Variables for Group Instance edn_cs_cmd_response_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csrng_rsp_sts_cg 5 0 5 100.00 100 1 1 0


Summary for Variable cp_csrng_rsp_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_csrng_rsp_sts_cg

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[CMD_STS_UNDRIVEN] 0 Excluded
undriven 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 7970 1 T1 3 T2 3 T3 4
auto[CMD_STS_INVALID_ACMD] 49 1 T45 1 T132 1 T133 1
auto[CMD_STS_INVALID_GEN_CMD] 44 1 T30 1 T111 1 T143 1
auto[CMD_STS_INVALID_CMD_SEQ] 51 1 T12 1 T85 1 T168 1
auto[CMD_STS_RESEED_CNT_EXCEEDED] 56 1 T17 1 T46 1 T131 1

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