Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

315105

1

T1

9

T2

6

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	201052	1			T1	25		T2	21		T3	58
values[0x0]	126225	1			T1	1		T2	6		T3	11
values[0x1]	141414	1			T1	7		T2	4		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	102959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

365732

1

T1

15

T2

13

T3

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1581	1			T5	1		T6	2		T94	7
valid_sources[0x01]	1497	1			T6	5		T77	2		T16	1
valid_sources[0x02]	2162	1			T6	2		T16	1		T66	36
valid_sources[0x03]	1628	1			T6	3		T20	2		T18	2
valid_sources[0x04]	1934	1			T27	1		T16	10		T45	2
valid_sources[0x05]	1757	1			T5	2		T6	5		T16	5
valid_sources[0x06]	1861	1			T6	1		T7	1		T16	6
valid_sources[0x07]	1788	1			T17	2		T6	2		T16	5
valid_sources[0x08]	1844	1			T6	3		T11	1		T41	1
valid_sources[0x09]	1701	1			T6	5		T11	1		T18	1
valid_sources[0x0a]	2066	1			T6	4		T11	1		T18	1
valid_sources[0x0b]	1712	1			T6	4		T33	1		T18	5
valid_sources[0x0c]	1677	1			T6	6		T33	1		T7	1
valid_sources[0x0d]	1833	1			T6	3		T33	1		T73	1
valid_sources[0x0e]	3149	1			T2	1		T6	5		T27	3
valid_sources[0x0f]	1789	1			T2	1		T6	1		T18	3
valid_sources[0x10]	2712	1			T17	2		T6	4		T7	2
valid_sources[0x11]	2138	1			T6	3		T11	1		T20	1
valid_sources[0x12]	1801	1			T6	3		T11	1		T33	1
valid_sources[0x13]	1703	1			T6	3		T28	3		T16	6
valid_sources[0x14]	1767	1			T4	2		T6	3		T11	1
valid_sources[0x15]	1839	1			T2	1		T23	1		T6	3
valid_sources[0x16]	1604	1			T23	1		T6	3		T7	3
valid_sources[0x17]	1535	1			T4	2		T6	8		T16	1
valid_sources[0x18]	1826	1			T6	4		T73	1		T18	2
valid_sources[0x19]	1866	1			T17	10		T6	2		T11	1
valid_sources[0x1a]	2044	1			T6	4		T11	2		T16	4
valid_sources[0x1b]	1771	1			T6	6		T18	2		T59	1
valid_sources[0x1c]	1594	1			T6	3		T20	1		T16	1
valid_sources[0x1d]	2000	1			T2	1		T5	3		T6	7
valid_sources[0x1e]	1515	1			T2	1		T6	10		T73	1
valid_sources[0x1f]	2018	1			T4	1		T6	9		T75	7
valid_sources[0x20]	1865	1			T2	1		T17	1		T6	3
valid_sources[0x21]	1886	1			T6	4		T12	1		T16	4
valid_sources[0x22]	1561	1			T2	1		T26	3		T6	3
valid_sources[0x23]	2612	1			T2	1		T6	5		T16	1
valid_sources[0x24]	2961	1			T6	4		T18	1		T9	1
valid_sources[0x25]	1888	1			T6	4		T33	2		T20	3
valid_sources[0x26]	2176	1			T6	2		T45	2		T123	6
valid_sources[0x27]	1600	1			T17	1		T6	5		T94	5
valid_sources[0x28]	1762	1			T17	1		T6	3		T16	4
valid_sources[0x29]	1972	1			T6	7		T7	2		T18	2
valid_sources[0x2a]	1937	1			T6	1		T11	1		T20	5
valid_sources[0x2b]	1726	1			T6	6		T73	2		T18	1
valid_sources[0x2c]	1770	1			T6	5		T33	2		T7	1
valid_sources[0x2d]	1630	1			T6	7		T27	1		T16	1
valid_sources[0x2e]	1595	1			T17	1		T6	3		T33	2
valid_sources[0x2f]	1739	1			T6	6		T18	2		T45	3
valid_sources[0x30]	1886	1			T6	5		T33	1		T77	2
valid_sources[0x31]	1963	1			T6	6		T11	2		T16	5
valid_sources[0x32]	1801	1			T17	2		T6	6		T11	1
valid_sources[0x33]	1880	1			T6	6		T33	1		T16	2
valid_sources[0x34]	1952	1			T2	1		T6	3		T11	1
valid_sources[0x35]	1755	1			T6	3		T33	1		T18	6
valid_sources[0x36]	1806	1			T6	6		T41	3		T73	1
valid_sources[0x37]	1612	1			T23	1		T17	2		T11	3
valid_sources[0x38]	1565	1			T6	4		T16	4		T18	2
valid_sources[0x39]	2870	1			T6	4		T33	1		T18	2
valid_sources[0x3a]	1642	1			T5	1		T6	4		T33	1
valid_sources[0x3b]	1832	1			T4	1		T6	3		T11	1
valid_sources[0x3c]	1719	1			T2	1		T5	2		T6	10
valid_sources[0x3d]	2087	1			T6	4		T77	1		T27	1
valid_sources[0x3e]	1614	1			T17	1		T24	45		T6	2
valid_sources[0x3f]	1591	1			T6	2		T72	1		T9	1
valid_sources[0x40]	1706	1			T6	4		T7	1		T18	1
valid_sources[0x41]	1782	1			T6	2		T20	1		T16	8
valid_sources[0x42]	1722	1			T6	1		T33	1		T18	1
valid_sources[0x43]	1663	1			T17	1		T6	4		T33	2
valid_sources[0x44]	1808	1			T6	3		T66	6		T18	1
valid_sources[0x45]	1728	1			T6	7		T11	2		T16	4
valid_sources[0x46]	1866	1			T2	1		T6	12		T27	1
valid_sources[0x47]	2134	1			T6	3		T11	1		T16	4
valid_sources[0x48]	1955	1			T6	1		T73	1		T74	1
valid_sources[0x49]	2263	1			T6	3		T7	1		T77	1
valid_sources[0x4a]	1560	1			T2	1		T6	3		T11	1
valid_sources[0x4b]	1902	1			T17	1		T6	4		T16	1
valid_sources[0x4c]	1806	1			T17	8		T6	3		T33	1
valid_sources[0x4d]	2159	1			T6	4		T16	1		T18	1
valid_sources[0x4e]	1638	1			T6	5		T7	1		T16	7
valid_sources[0x4f]	1705	1			T2	1		T6	4		T16	5
valid_sources[0x50]	1850	1			T5	1		T6	3		T77	3
valid_sources[0x51]	1864	1			T4	1		T17	2		T6	2
valid_sources[0x52]	1964	1			T17	1		T6	7		T16	2
valid_sources[0x53]	1527	1			T6	5		T18	2		T106	3
valid_sources[0x54]	1599	1			T6	8		T16	1		T18	2
valid_sources[0x55]	1916	1			T6	2		T7	2		T20	3
valid_sources[0x56]	2173	1			T6	6		T33	1		T16	2
valid_sources[0x57]	1586	1			T17	1		T6	4		T11	1
valid_sources[0x58]	2238	1			T6	4		T72	1		T73	1
valid_sources[0x59]	1651	1			T23	1		T6	3		T20	7
valid_sources[0x5a]	1733	1			T6	3		T16	1		T74	1
valid_sources[0x5b]	1633	1			T6	7		T11	1		T75	7
valid_sources[0x5c]	1887	1			T6	7		T7	1		T16	3
valid_sources[0x5d]	1440	1			T6	5		T7	1		T72	1
valid_sources[0x5e]	1804	1			T26	1		T6	6		T16	5
valid_sources[0x5f]	1673	1			T6	6		T16	6		T18	1
valid_sources[0x60]	1769	1			T6	1		T18	1		T21	2
valid_sources[0x61]	1897	1			T17	1		T6	2		T7	4
valid_sources[0x62]	1631	1			T6	3		T41	1		T73	1
valid_sources[0x63]	1699	1			T25	4		T6	5		T11	3
valid_sources[0x64]	2205	1			T6	4		T11	1		T41	1
valid_sources[0x65]	1689	1			T6	3		T11	1		T21	1
valid_sources[0x66]	1825	1			T10	48		T6	2		T11	1
valid_sources[0x67]	1607	1			T2	1		T6	3		T18	2
valid_sources[0x68]	1668	1			T5	1		T6	5		T11	1
valid_sources[0x69]	1538	1			T6	8		T11	1		T73	1
valid_sources[0x6a]	1489	1			T26	5		T6	7		T77	1
valid_sources[0x6b]	1784	1			T17	1		T26	4		T6	1
valid_sources[0x6c]	1637	1			T5	1		T26	1		T6	3
valid_sources[0x6d]	1770	1			T6	13		T94	13		T16	1
valid_sources[0x6e]	1504	1			T11	1		T18	2		T45	1
valid_sources[0x6f]	1716	1			T6	2		T33	1		T73	1
valid_sources[0x70]	1785	1			T6	5		T75	7		T18	3
valid_sources[0x71]	2754	1			T6	4		T7	2		T27	1
valid_sources[0x72]	1835	1			T6	7		T7	1		T16	1
valid_sources[0x73]	1870	1			T2	1		T17	1		T6	3
valid_sources[0x74]	1586	1			T6	1		T27	9		T16	6
valid_sources[0x75]	1710	1			T2	1		T6	6		T41	2
valid_sources[0x76]	1886	1			T6	5		T18	2		T123	3
valid_sources[0x77]	1816	1			T17	1		T6	4		T16	3
valid_sources[0x78]	1680	1			T6	5		T16	1		T66	14
valid_sources[0x79]	1872	1			T4	3		T6	5		T11	3
valid_sources[0x7a]	1724	1			T6	1		T11	2		T7	1
valid_sources[0x7b]	2114	1			T6	13		T33	2		T27	3
valid_sources[0x7c]	1531	1			T6	3		T16	1		T73	1
valid_sources[0x7d]	1509	1			T6	5		T16	12		T66	14
valid_sources[0x7e]	1977	1			T23	2		T6	1		T11	1
valid_sources[0x7f]	1467	1			T6	5		T11	1		T16	8
valid_sources[0x80]	1835	1			T17	1		T6	2		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85022

1

T1

5

T2

2

T3

4

values[0x0]

all_enables

biggest_size

115855

1

T2

3

T3

10

T23

2

values[0x1]

all_enables

biggest_size

114228

1

T1

4

T2

1

T3

14