Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1804	1			T3	2		T10	5		T6	10
non_zero_bins[1]	1215	1			T3	1		T6	6		T11	4
zero	6332	1			T1	3		T2	3		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	295	1			T3	1		T6	2		T123	2
uni	2261	1			T1	1		T2	1		T3	1
gen	3171	1			T1	1		T2	1		T3	1
res	641	1			T10	4		T6	2		T11	2
ins	2983	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6028

1

T1

3

T2

2

T3

3

mubi_true

3323

1

T2

1

T3

1

T17

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

37

1

T132

1

T310

1

T178

1

pass

9314

1

T1

3

T2

3

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	63	1			T3	1		T6	2		T123	1
upd	non_zero_bins[0]	pass	mubi_true	64	1			T123	1		T121	1		T116	1
upd	non_zero_bins[1]	pass	mubi_false	44	1			T116	1		T39	1		T233	1
upd	non_zero_bins[1]	pass	mubi_true	44	1			T39	3		T54	1		T311	1
upd	zero	pass	mubi_false	35	1			T43	1		T121	1		T60	1
upd	zero	pass	mubi_true	45	1			T120	1		T121	1		T312	1
uni	zero	pass	mubi_false	1722	1			T1	1		T3	1		T26	1
uni	zero	pass	mubi_true	539	1			T2	1		T25	1		T6	1
gen	non_zero_bins[0]	pass	mubi_false	323	1			T3	1		T6	2		T64	1
gen	non_zero_bins[0]	pass	mubi_true	402	1			T6	1		T66	1		T21	3
gen	non_zero_bins[1]	pass	mubi_false	258	1			T6	1		T11	3		T66	1
gen	non_zero_bins[1]	pass	mubi_true	207	1			T6	1		T11	1		T64	1
gen	zero	fail	mubi_false	32	1			T132	1		T310	1		T255	1
gen	zero	pass	mubi_false	1299	1			T1	1		T2	1		T23	1
gen	zero	pass	mubi_true	650	1			T17	2		T6	1		T28	1
res	non_zero_bins[0]	pass	mubi_false	153	1			T10	4		T6	1		T66	1
res	non_zero_bins[0]	pass	mubi_true	150	1			T6	1		T11	2		T51	4
res	non_zero_bins[1]	pass	mubi_false	102	1			T64	1		T21	3		T105	1
res	non_zero_bins[1]	pass	mubi_true	83	1			T20	1		T66	2		T53	3
res	zero	fail	mubi_false	5	1			T178	1		T179	1		T180	1
res	zero	pass	mubi_false	84	1			T12	1		T7	1		T143	1
res	zero	pass	mubi_true	64	1			T41	2		T48	2		T13	2
ins	non_zero_bins[0]	pass	mubi_false	328	1			T10	1		T6	2		T20	1
ins	non_zero_bins[0]	pass	mubi_true	321	1			T6	1		T11	1		T66	1
ins	non_zero_bins[1]	pass	mubi_false	228	1			T6	4		T313	1		T48	1
ins	non_zero_bins[1]	pass	mubi_true	249	1			T3	1		T64	2		T20	1
ins	zero	pass	mubi_false	1352	1			T1	1		T2	1		T23	1
ins	zero	pass	mubi_true	505	1			T17	1		T12	1		T64	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded