Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.20 100.00 90.59 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[10].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[11].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[12].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[13].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[14].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[15].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[16].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[17].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[18].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[19].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[5].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[6].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[7].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[8].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[9].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.20 100.00 90.59 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.20 100.00 90.59 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.20 100.00 90.59 98.23 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=20,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

Line No.TotalCoveredPercent
TOTAL2121100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 20/20 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=4,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 4/4 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

SCORELINE
100.00 100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 3788 3788 0 0
OutputsKnown_A 45959416 45242396 0 0
gen_no_flops.OutputDelay_A 45959416 45242396 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3788 3788 0 0
T1 4 4 0 0
T2 4 4 0 0
T3 4 4 0 0
T4 4 4 0 0
T5 4 4 0 0
T10 4 4 0 0
T17 4 4 0 0
T23 4 4 0 0
T24 4 4 0 0
T25 4 4 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 45959416 45242396 0 0
T1 4492 4180 0 0
T2 6364 6052 0 0
T3 10196 9844 0 0
T4 2208 1420 0 0
T5 8944 8352 0 0
T10 10228 9952 0 0
T17 11740 11460 0 0
T23 3920 3680 0 0
T24 4748 4480 0 0
T25 3656 3400 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 45959416 45242396 0 0
T1 4492 4180 0 0
T2 6364 6052 0 0
T3 10196 9844 0 0
T4 2208 1420 0 0
T5 8944 8352 0 0
T10 10228 9952 0 0
T17 11740 11460 0 0
T23 3920 3680 0 0
T24 4748 4480 0 0
T25 3656 3400 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable
Line No.TotalCoveredPercent
TOTAL2121100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 20/20 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 947 947 0 0
OutputsKnown_A 11489854 11310599 0 0
gen_no_flops.OutputDelay_A 11489854 11310599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 947 947 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 4/4 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 947 947 0 0
OutputsKnown_A 11489854 11310599 0 0
gen_no_flops.OutputDelay_A 11489854 11310599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 947 947 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 947 947 0 0
OutputsKnown_A 11489854 11310599 0 0
gen_no_flops.OutputDelay_A 11489854 11310599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 947 947 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi4False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi4Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 2/2 assign mubi_o[j] = mubi4_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 947 947 0 0
OutputsKnown_A 11489854 11310599 0 0
gen_no_flops.OutputDelay_A 11489854 11310599 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 947 947 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11489854 11310599 0 0
T1 1123 1045 0 0
T2 1591 1513 0 0
T3 2549 2461 0 0
T4 552 355 0 0
T5 2236 2088 0 0
T10 2557 2488 0 0
T17 2935 2865 0 0
T23 980 920 0 0
T24 1187 1120 0 0
T25 914 850 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%