Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	142	1			T23	1		T26	1		T37	1
auto_req_mode	142	1			T11	1		T18	1		T38	1
sw_mode	1764	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

302

1

T3

1

T11

1

T26

1

single

98

1

T23

1

T18

1

T65

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	819	1			T1	1		T3	1		T23	1
auto[2]	76	1			T70	1		T308	1		T309	12
auto[3]	35	1			T26	1		T243	5		T284	11
auto[4]	96	1			T310	6		T80	1		T311	20
auto[5]	75	1			T71	1		T304	7		T79	1
auto[6]	24	1			T101	11		T312	6		T313	1
auto[7]	923	1			T2	1		T5	7		T40	10

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	90	1			T23	1		T37	1		T39	1
auto[1]	auto_req_mode	83	1			T11	1		T18	1		T38	1
auto[1]	sw_mode	646	1			T1	1		T3	1		T24	1
auto[2]	boot_req_mode	3	1			T314	1		T315	1		T316	1
auto[2]	auto_req_mode	5	1			T308	1		T254	1		T317	1
auto[2]	sw_mode	68	1			T70	1		T309	12		T318	3
auto[3]	boot_req_mode	2	1			T26	1		T319	1		-	-
auto[3]	auto_req_mode	5	1			T320	1		T321	1		T322	1
auto[3]	sw_mode	28	1			T243	5		T284	11		T323	6
auto[4]	boot_req_mode	8	1			T80	1		T324	1		T325	1
auto[4]	auto_req_mode	1	1			T326	1		-	-		-	-
auto[4]	sw_mode	87	1			T310	6		T311	20		T327	1
auto[5]	boot_req_mode	3	1			T71	1		T79	1		T328	1
auto[5]	auto_req_mode	4	1			T329	1		T330	1		T331	1
auto[5]	sw_mode	68	1			T304	7		T244	5		T332	2
auto[6]	boot_req_mode	2	1			T333	1		T334	1		-	-
auto[6]	auto_req_mode	3	1			T335	1		T336	1		T337	1
auto[6]	sw_mode	19	1			T101	11		T312	6		T313	1
auto[7]	boot_req_mode	34	1			T49	1		T338	1		T339	1
auto[7]	auto_req_mode	41	1			T43	1		T45	1		T13	1
auto[7]	sw_mode	848	1			T2	1		T5	7		T40	10