Group : tb.dut.u_edn_cov_if::edn_error_cg
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Group : tb.dut.u_edn_cov_if::edn_error_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
87.50 87.50 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_error_cg 87.50 1 100 1 64 64




Group Instance : edn_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance edn_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group Instance edn_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error_test 8 1 7 87.50 100 1 1 0


Summary for Variable cp_error_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 1 7 87.50


Automatically Generated Bins for cp_error_test

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[EdnFifoReadErrTest] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[EdnSfifoRescmdErrTest] 27 1 T16 3 T17 9 T19 3
auto[EdnSfifoGencmdErrTest] 18 1 T16 5 T17 6 T19 1
auto[EdnAckSmErrTest] 1010 1 T6 1 T16 130 T62 1
auto[EdnMainSmErrTest] 1010 1 T6 1 T16 130 T62 1
auto[EdnCntrErrTest] 101 1 T16 10 T7 1 T17 20
auto[EdnFifoWriteErrTest] 1 1 T94 1 - - - -
auto[EdnFifoStateErrTest] 44 1 T16 8 T17 15 T19 4

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