Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
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Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
66.67 66.67 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_sw_cmd_sts_cg 66.67 1 100 1 64 64




Group Instance : edn_sw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
66.67 1 100 1 64 64




Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 4 8 66.67


Variables for Group Instance edn_sw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_cmd_ack_cg 2 0 2 100.00 100 1 1 0
cp_cmd_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_reg_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_sts_cg 6 4 2 33.33 100 1 1 0


Summary for Variable cp_cmd_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 15532 1 T1 1 T2 1 T3 16
ack 11003 1 T1 5 T2 5 T3 7



Summary for Variable cp_cmd_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 14854 1 T3 15 T5 30 T11 3
ready 11681 1 T1 6 T2 6 T3 8



Summary for Variable cp_cmd_reg_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_reg_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 357 1 T11 1 T18 1 T38 2
ready 26178 1 T1 6 T2 6 T3 23



Summary for Variable cp_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 4 2 33.33


Automatically Generated Bins for cp_cmd_sts_cg

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[CMD_STS_INVALID_ACMD] 0 1 1
auto[CMD_STS_INVALID_GEN_CMD] 0 1 1
auto[CMD_STS_INVALID_CMD_SEQ] 0 1 1
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 26534 1 T1 6 T2 6 T3 23
auto[CMD_STS_RESEED_CNT_EXCEEDED] 1 1 T278 1 - - - -

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