Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

286919

1

T1

6

T2

12

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	186874	1			T1	17		T2	45		T3	65
values[0x0]	115567	1			T1	3		T2	5		T3	8
values[0x1]	128675	1			T1	4		T2	4		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	96931	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

334185

1

T1

14

T2

26

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1627	1			T57	1		T16	1		T40	2
valid_sources[0x01]	1516	1			T3	3		T40	3		T64	2
valid_sources[0x02]	1500	1			T5	2		T16	2		T12	4
valid_sources[0x03]	2707	1			T2	1		T5	1		T16	1
valid_sources[0x04]	1464	1			T5	2		T16	1		T40	6
valid_sources[0x05]	1693	1			T5	5		T16	3		T40	7
valid_sources[0x06]	1148	1			T16	1		T18	8		T42	1
valid_sources[0x07]	1775	1			T1	1		T16	1		T40	2
valid_sources[0x08]	1473	1			T1	1		T5	1		T16	1
valid_sources[0x09]	2074	1			T2	1		T3	1		T5	1
valid_sources[0x0a]	1359	1			T5	5		T40	4		T41	2
valid_sources[0x0b]	1813	1			T5	9		T40	7		T18	1
valid_sources[0x0c]	1320	1			T2	1		T10	1		T5	9
valid_sources[0x0d]	1425	1			T5	2		T16	1		T12	1
valid_sources[0x0e]	1654	1			T2	1		T16	4		T12	2
valid_sources[0x0f]	1373	1			T1	1		T3	1		T5	8
valid_sources[0x10]	1695	1			T40	1		T25	2		T55	4
valid_sources[0x11]	2136	1			T5	1		T40	7		T25	1
valid_sources[0x12]	1707	1			T5	3		T40	11		T41	14
valid_sources[0x13]	1304	1			T3	1		T5	3		T16	2
valid_sources[0x14]	1382	1			T2	1		T16	2		T40	4
valid_sources[0x15]	2171	1			T5	5		T16	1		T40	8
valid_sources[0x16]	2311	1			T5	3		T24	5		T16	1
valid_sources[0x17]	1670	1			T5	6		T16	1		T12	10
valid_sources[0x18]	1691	1			T2	1		T3	3		T5	3
valid_sources[0x19]	1669	1			T1	1		T3	1		T5	2
valid_sources[0x1a]	1352	1			T40	4		T17	8		T43	1
valid_sources[0x1b]	1831	1			T5	2		T16	1		T40	2
valid_sources[0x1c]	1593	1			T3	1		T5	4		T16	3
valid_sources[0x1d]	1612	1			T3	1		T5	6		T16	3
valid_sources[0x1e]	1589	1			T3	1		T5	2		T40	7
valid_sources[0x1f]	1531	1			T3	4		T16	1		T40	1
valid_sources[0x20]	1683	1			T5	1		T16	3		T40	6
valid_sources[0x21]	1565	1			T10	2		T5	2		T16	1
valid_sources[0x22]	1297	1			T5	6		T16	2		T12	2
valid_sources[0x23]	1760	1			T5	6		T57	1		T16	4
valid_sources[0x24]	1812	1			T5	3		T12	2		T40	1
valid_sources[0x25]	1506	1			T2	1		T10	2		T5	1
valid_sources[0x26]	1725	1			T5	4		T16	5		T40	1
valid_sources[0x27]	1533	1			T5	6		T16	3		T40	2
valid_sources[0x28]	1605	1			T5	4		T16	1		T40	8
valid_sources[0x29]	1408	1			T4	1		T10	1		T5	4
valid_sources[0x2a]	1706	1			T5	9		T16	2		T40	3
valid_sources[0x2b]	1358	1			T4	2		T5	3		T40	2
valid_sources[0x2c]	1924	1			T3	1		T16	1		T12	1
valid_sources[0x2d]	2211	1			T3	2		T5	1		T16	1
valid_sources[0x2e]	1223	1			T3	1		T5	4		T16	3
valid_sources[0x2f]	1253	1			T5	2		T16	5		T40	4
valid_sources[0x30]	1694	1			T10	1		T5	6		T40	4
valid_sources[0x31]	1546	1			T5	2		T16	3		T40	2
valid_sources[0x32]	1626	1			T2	1		T16	1		T40	4
valid_sources[0x33]	2117	1			T2	1		T5	2		T16	3
valid_sources[0x34]	1596	1			T5	1		T16	1		T40	5
valid_sources[0x35]	1337	1			T10	4		T5	3		T40	3
valid_sources[0x36]	1568	1			T5	5		T16	3		T40	2
valid_sources[0x37]	1397	1			T1	1		T10	1		T5	10
valid_sources[0x38]	1435	1			T3	1		T5	3		T16	2
valid_sources[0x39]	1400	1			T40	2		T41	3		T55	1
valid_sources[0x3a]	1463	1			T3	2		T5	2		T16	1
valid_sources[0x3b]	2185	1			T40	3		T41	8		T17	5
valid_sources[0x3c]	1987	1			T4	1		T40	6		T37	5
valid_sources[0x3d]	1410	1			T16	3		T40	3		T41	6
valid_sources[0x3e]	2182	1			T10	3		T5	2		T6	19
valid_sources[0x3f]	1358	1			T2	2		T5	6		T16	2
valid_sources[0x40]	2532	1			T4	2		T16	1		T40	7
valid_sources[0x41]	1366	1			T16	3		T40	9		T67	3
valid_sources[0x42]	2377	1			T3	1		T5	8		T16	3
valid_sources[0x43]	1161	1			T40	4		T41	4		T43	1
valid_sources[0x44]	1583	1			T5	1		T40	4		T89	1
valid_sources[0x45]	2248	1			T5	2		T16	3		T40	4
valid_sources[0x46]	1410	1			T5	1		T16	3		T40	3
valid_sources[0x47]	1614	1			T5	1		T40	3		T7	2
valid_sources[0x48]	2007	1			T2	2		T5	4		T16	3
valid_sources[0x49]	2149	1			T5	5		T16	1		T40	1
valid_sources[0x4a]	1486	1			T2	1		T3	1		T5	7
valid_sources[0x4b]	2094	1			T4	3		T5	1		T24	3
valid_sources[0x4c]	1719	1			T5	4		T40	3		T43	1
valid_sources[0x4d]	1942	1			T5	7		T43	1		T102	1
valid_sources[0x4e]	1997	1			T1	1		T5	3		T16	4
valid_sources[0x4f]	2161	1			T5	3		T16	3		T40	3
valid_sources[0x50]	1312	1			T5	8		T16	4		T40	3
valid_sources[0x51]	2150	1			T5	1		T16	1		T12	3
valid_sources[0x52]	1580	1			T5	3		T16	2		T40	5
valid_sources[0x53]	1746	1			T5	5		T16	4		T40	2
valid_sources[0x54]	1706	1			T2	1		T10	1		T12	1
valid_sources[0x55]	1702	1			T5	1		T16	2		T40	4
valid_sources[0x56]	1356	1			T3	3		T16	3		T40	1
valid_sources[0x57]	1723	1			T102	2		T34	17		T58	2
valid_sources[0x58]	1714	1			T3	1		T10	1		T5	7
valid_sources[0x59]	1509	1			T3	2		T5	5		T16	3
valid_sources[0x5a]	1701	1			T5	5		T16	1		T40	4
valid_sources[0x5b]	1981	1			T1	1		T5	3		T16	1
valid_sources[0x5c]	1564	1			T5	4		T16	1		T40	4
valid_sources[0x5d]	1606	1			T16	1		T40	5		T41	2
valid_sources[0x5e]	1806	1			T5	1		T16	1		T40	4
valid_sources[0x5f]	2303	1			T5	1		T24	14		T16	3
valid_sources[0x60]	1412	1			T2	1		T4	2		T12	1
valid_sources[0x61]	1192	1			T2	1		T5	1		T57	1
valid_sources[0x62]	1476	1			T5	15		T16	3		T40	2
valid_sources[0x63]	1540	1			T2	2		T5	2		T40	3
valid_sources[0x64]	1486	1			T5	2		T16	2		T40	1
valid_sources[0x65]	1795	1			T3	1		T5	1		T16	1
valid_sources[0x66]	1318	1			T1	2		T5	1		T57	2
valid_sources[0x67]	2285	1			T2	1		T5	4		T16	1
valid_sources[0x68]	1351	1			T1	1		T40	5		T41	1
valid_sources[0x69]	1487	1			T16	2		T40	3		T25	1
valid_sources[0x6a]	1752	1			T5	2		T40	2		T17	3
valid_sources[0x6b]	1409	1			T16	2		T25	2		T41	4
valid_sources[0x6c]	2609	1			T5	1		T40	5		T25	1
valid_sources[0x6d]	1743	1			T5	5		T16	1		T40	8
valid_sources[0x6e]	2259	1			T5	2		T16	2		T40	2
valid_sources[0x6f]	1748	1			T40	2		T17	3		T8	1
valid_sources[0x70]	3002	1			T5	5		T40	2		T41	1
valid_sources[0x71]	1823	1			T1	1		T3	1		T16	7
valid_sources[0x72]	1571	1			T5	1		T57	1		T41	3
valid_sources[0x73]	1474	1			T4	1		T5	1		T16	4
valid_sources[0x74]	2286	1			T5	1		T16	1		T40	2
valid_sources[0x75]	1782	1			T3	1		T5	1		T12	4
valid_sources[0x76]	1766	1			T3	1		T4	1		T10	11
valid_sources[0x77]	1271	1			T16	2		T40	2		T41	1
valid_sources[0x78]	1692	1			T5	4		T16	4		T40	2
valid_sources[0x79]	1306	1			T10	2		T5	4		T12	1
valid_sources[0x7a]	1453	1			T2	1		T5	3		T16	3
valid_sources[0x7b]	1343	1			T3	1		T40	8		T64	1
valid_sources[0x7c]	1250	1			T16	1		T40	5		T17	1
valid_sources[0x7d]	1447	1			T16	1		T40	2		T41	3
valid_sources[0x7e]	1870	1			T3	1		T16	2		T40	4
valid_sources[0x7f]	1508	1			T3	1		T5	8		T16	1
valid_sources[0x80]	1460	1			T1	2		T16	5		T40	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77716

1

T1

3

T2

6

T3

7

values[0x0]

all_enables

biggest_size

105718

1

T1

1

T2

3

T3

8

values[0x1]

all_enables

biggest_size

103485

1

T1

2

T2

3

T3

11