Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1727	1			T3	1		T5	3		T11	1
non_zero_bins[1]	1229	1			T3	1		T5	2		T11	6
zero	5662	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	305	1			T5	1		T40	3		T41	1
uni	1977	1			T1	1		T2	1		T3	1
gen	2958	1			T1	1		T2	1		T3	1
res	629	1			T3	1		T10	1		T11	3
ins	2749	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5346

1

T1

2

T2

3

T3

4

mubi_true

3272

1

T1

1

T10

3

T23

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

36

1

T25

1

T56

1

T112

1

pass

8582

1

T1

3

T2

3

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	69	1			T102	1		T34	2		T100	1
upd	non_zero_bins[0]	pass	mubi_true	75	1			T41	1		T102	1		T34	1
upd	non_zero_bins[1]	pass	mubi_false	56	1			T40	2		T108	1		T35	1
upd	non_zero_bins[1]	pass	mubi_true	45	1			T5	1		T40	1		T100	1
upd	zero	pass	mubi_false	27	1			T283	1		T241	1		T36	1
upd	zero	pass	mubi_true	33	1			T102	1		T101	1		T284	1
uni	zero	pass	mubi_false	1509	1			T2	1		T3	1		T10	1
uni	zero	pass	mubi_true	468	1			T1	1		T5	2		T26	1
gen	non_zero_bins[0]	pass	mubi_false	328	1			T5	1		T40	1		T41	1
gen	non_zero_bins[0]	pass	mubi_true	354	1			T65	1		T102	2		T34	2
gen	non_zero_bins[1]	pass	mubi_false	235	1			T11	3		T40	3		T41	1
gen	non_zero_bins[1]	pass	mubi_true	242	1			T5	1		T40	1		T45	1
gen	zero	fail	mubi_false	33	1			T25	1		T56	1		T112	1
gen	zero	pass	mubi_false	1079	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	687	1			T10	2		T23	1		T26	2
res	non_zero_bins[0]	pass	mubi_false	155	1			T3	1		T18	5		T65	1
res	non_zero_bins[0]	pass	mubi_true	142	1			T20	6		T45	2		T285	1
res	non_zero_bins[1]	pass	mubi_false	113	1			T102	2		T100	2		T106	1
res	non_zero_bins[1]	pass	mubi_true	95	1			T11	3		T21	3		T100	1
res	zero	fail	mubi_false	3	1			T157	1		T286	1		T287	1
res	zero	pass	mubi_false	72	1			T10	1		T12	1		T40	1
res	zero	pass	mubi_true	49	1			T40	1		T43	2		T102	2
ins	non_zero_bins[0]	pass	mubi_false	282	1			T5	1		T102	3		T34	2
ins	non_zero_bins[0]	pass	mubi_true	322	1			T5	1		T11	1		T26	1
ins	non_zero_bins[1]	pass	mubi_false	217	1			T3	1		T20	1		T102	2
ins	non_zero_bins[1]	pass	mubi_true	226	1			T40	1		T18	1		T102	1
ins	zero	pass	mubi_false	1168	1			T1	1		T2	1		T4	1
ins	zero	pass	mubi_true	534	1			T10	1		T23	1		T6	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded