Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	141	1			T21	1		T24	1		T25	1
auto_req_mode	138	1			T9	1		T11	1		T19	1
sw_mode	2094	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

298

1

T9

1

T21

1

T11

1

single

102

1

T19

1

T49

1

T50

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	840	1			T1	1		T9	1		T21	1
auto[2]	127	1			T2	1		T312	1		T324	10
auto[3]	90	1			T80	1		T244	28		T325	1
auto[4]	131	1			T11	1		T128	10		T76	1
auto[5]	75	1			T49	1		T326	1		T327	4
auto[6]	148	1			T321	1		T119	4		T44	1
auto[7]	962	1			T3	1		T23	1		T27	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	88	1			T21	1		T24	1		T25	1
auto[1]	auto_req_mode	83	1			T9	1		T19	1		T38	1
auto[1]	sw_mode	669	1			T1	1		T70	1		T66	1
auto[2]	boot_req_mode	4	1			T328	1		T329	1		T330	1
auto[2]	auto_req_mode	9	1			T312	1		T331	1		T332	1
auto[2]	sw_mode	114	1			T2	1		T324	10		T333	1
auto[3]	boot_req_mode	4	1			T334	1		T335	1		T336	1
auto[3]	auto_req_mode	5	1			T325	1		T337	1		T338	1
auto[3]	sw_mode	81	1			T80	1		T244	28		T339	50
auto[4]	boot_req_mode	7	1			T340	1		T341	1		T342	1
auto[4]	auto_req_mode	2	1			T11	1		T343	1		-	-
auto[4]	sw_mode	122	1			T128	10		T76	1		T344	1
auto[5]	boot_req_mode	2	1			T345	1		T346	1		-	-
auto[5]	auto_req_mode	7	1			T49	1		T347	1		T348	1
auto[5]	sw_mode	66	1			T326	1		T327	4		T349	1
auto[6]	boot_req_mode	6	1			T350	1		T351	1		T352	1
auto[6]	auto_req_mode	4	1			T353	1		T354	1		T355	1
auto[6]	sw_mode	138	1			T321	1		T119	4		T44	1
auto[7]	boot_req_mode	30	1			T54	1		T56	1		T356	1
auto[7]	auto_req_mode	28	1			T20	1		T12	1		T13	1
auto[7]	sw_mode	904	1			T3	1		T23	1		T27	1