Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_endpoint_err_req_cg 100.00 1 100 1 64 64




Group Instance : edn_endpoint_err_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_endpoint_err_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance edn_endpoint_err_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
endpoint_cg 7 0 7 100.00 100 1 1 0


Summary for Variable endpoint_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for endpoint_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
range[0x0] 535 1 T16 74 T17 55 T18 131
range[0x1] 497 1 T16 59 T17 63 T18 115
range[0x2] 542 1 T16 71 T17 61 T18 134
range[0x3] 521 1 T16 64 T17 65 T18 127
range[0x4] 500 1 T16 65 T17 73 T18 114
range[0x5] 533 1 T16 69 T17 61 T18 127
range[0x6] 511 1 T16 53 T17 71 T18 121

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%