Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

337863

1

T1

9

T2

9

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	208864	1			T1	20		T2	20		T3	74
values[0x0]	135479	1			T1	3		T2	4		T3	9
values[0x1]	151347	1			T1	5		T2	6		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	105723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

389967

1

T1

16

T2

13

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1484	1			T27	1		T39	3		T40	2
valid_sources[0x01]	1538	1			T10	1		T23	4		T26	1
valid_sources[0x02]	1601	1			T3	1		T10	1		T39	1
valid_sources[0x03]	1466	1			T39	1		T41	3		T72	1
valid_sources[0x04]	2131	1			T27	1		T39	3		T114	1
valid_sources[0x05]	1581	1			T23	1		T19	2		T141	2
valid_sources[0x06]	1350	1			T66	1		T20	4		T41	1
valid_sources[0x07]	2600	1			T24	6		T19	2		T41	1
valid_sources[0x08]	2056	1			T10	1		T28	1		T19	1
valid_sources[0x09]	1677	1			T10	2		T70	1		T19	1
valid_sources[0x0a]	2424	1			T10	1		T70	1		T66	1
valid_sources[0x0b]	1450	1			T66	1		T39	1		T38	1
valid_sources[0x0c]	2330	1			T3	3		T27	5		T19	1
valid_sources[0x0d]	1968	1			T2	1		T19	1		T20	19
valid_sources[0x0e]	1846	1			T2	4		T3	1		T70	1
valid_sources[0x0f]	1836	1			T10	2		T66	1		T39	1
valid_sources[0x10]	1386	1			T5	1		T10	1		T39	1
valid_sources[0x11]	1832	1			T3	2		T15	3		T66	1
valid_sources[0x12]	1969	1			T70	1		T19	1		T39	3
valid_sources[0x13]	1962	1			T5	3		T27	1		T28	2
valid_sources[0x14]	1559	1			T10	1		T28	2		T39	3
valid_sources[0x15]	2291	1			T15	2		T41	1		T71	2
valid_sources[0x16]	1687	1			T5	3		T41	3		T141	1
valid_sources[0x17]	1565	1			T15	1		T66	1		T39	1
valid_sources[0x18]	2441	1			T3	1		T4	2		T10	1
valid_sources[0x19]	1951	1			T66	2		T39	2		T38	1
valid_sources[0x1a]	1446	1			T10	1		T39	2		T26	2
valid_sources[0x1b]	2076	1			T3	1		T27	2		T20	2
valid_sources[0x1c]	1996	1			T3	1		T39	3		T20	2
valid_sources[0x1d]	1327	1			T10	1		T22	2		T19	2
valid_sources[0x1e]	1876	1			T3	1		T15	1		T19	1
valid_sources[0x1f]	2121	1			T39	1		T7	8		T141	1
valid_sources[0x20]	2020	1			T3	2		T114	3		T63	2
valid_sources[0x21]	1748	1			T10	1		T70	2		T66	1
valid_sources[0x22]	1334	1			T22	1		T19	1		T39	2
valid_sources[0x23]	2323	1			T70	1		T27	1		T39	2
valid_sources[0x24]	1530	1			T3	1		T21	2		T41	1
valid_sources[0x25]	1832	1			T3	1		T10	1		T19	2
valid_sources[0x26]	1646	1			T10	1		T22	1		T27	1
valid_sources[0x27]	2034	1			T3	1		T70	1		T15	8
valid_sources[0x28]	1612	1			T66	1		T39	1		T114	2
valid_sources[0x29]	2056	1			T66	1		T38	2		T45	1
valid_sources[0x2a]	2222	1			T3	1		T27	1		T28	1
valid_sources[0x2b]	1362	1			T10	1		T22	1		T27	1
valid_sources[0x2c]	2274	1			T2	3		T136	36		T114	1
valid_sources[0x2d]	2042	1			T3	1		T21	2		T22	1
valid_sources[0x2e]	2150	1			T70	1		T27	1		T66	1
valid_sources[0x2f]	1897	1			T10	1		T27	1		T15	1
valid_sources[0x30]	1586	1			T3	1		T22	1		T39	1
valid_sources[0x31]	2475	1			T19	1		T39	1		T20	4
valid_sources[0x32]	3031	1			T23	8		T39	1		T41	4
valid_sources[0x33]	2560	1			T10	1		T22	1		T39	1
valid_sources[0x34]	1766	1			T5	1		T10	1		T27	1
valid_sources[0x35]	1738	1			T10	1		T27	1		T114	3
valid_sources[0x36]	2018	1			T3	2		T27	1		T19	1
valid_sources[0x37]	1771	1			T19	1		T39	1		T40	1
valid_sources[0x38]	1715	1			T4	3		T66	1		T39	3
valid_sources[0x39]	2278	1			T19	2		T41	3		T114	2
valid_sources[0x3a]	1806	1			T22	1		T70	1		T15	3
valid_sources[0x3b]	1753	1			T27	2		T19	2		T41	3
valid_sources[0x3c]	1720	1			T3	1		T22	1		T39	5
valid_sources[0x3d]	2089	1			T3	3		T39	2		T20	2
valid_sources[0x3e]	1862	1			T10	1		T22	1		T27	1
valid_sources[0x3f]	2047	1			T5	1		T15	2		T19	2
valid_sources[0x40]	1796	1			T15	4		T39	3		T114	3
valid_sources[0x41]	3160	1			T3	1		T27	1		T19	2
valid_sources[0x42]	3067	1			T27	1		T141	2		T114	7
valid_sources[0x43]	1766	1			T15	1		T39	3		T40	1
valid_sources[0x44]	2208	1			T3	2		T5	2		T10	1
valid_sources[0x45]	1471	1			T70	1		T23	1		T39	1
valid_sources[0x46]	1490	1			T71	1		T114	1		T86	2
valid_sources[0x47]	2138	1			T5	1		T10	1		T27	2
valid_sources[0x48]	2631	1			T15	3		T39	4		T40	1
valid_sources[0x49]	1780	1			T19	1		T39	2		T40	1
valid_sources[0x4a]	2039	1			T27	2		T19	1		T39	1
valid_sources[0x4b]	1549	1			T39	2		T88	1		T71	1
valid_sources[0x4c]	1811	1			T15	2		T19	2		T39	1
valid_sources[0x4d]	1690	1			T15	1		T19	2		T7	3
valid_sources[0x4e]	2013	1			T3	1		T27	1		T18	12
valid_sources[0x4f]	2145	1			T3	1		T10	1		T19	1
valid_sources[0x50]	1825	1			T66	1		T19	1		T7	1
valid_sources[0x51]	1663	1			T66	1		T38	3		T114	4
valid_sources[0x52]	1889	1			T66	1		T68	16		T41	1
valid_sources[0x53]	1788	1			T2	1		T10	1		T66	1
valid_sources[0x54]	2188	1			T2	2		T3	1		T39	2
valid_sources[0x55]	1991	1			T27	1		T20	8		T41	2
valid_sources[0x56]	1693	1			T10	2		T66	1		T39	1
valid_sources[0x57]	2268	1			T28	4		T15	6		T67	26
valid_sources[0x58]	1837	1			T3	2		T66	1		T39	1
valid_sources[0x59]	2408	1			T5	2		T27	2		T66	1
valid_sources[0x5a]	2257	1			T3	3		T10	2		T22	1
valid_sources[0x5b]	1668	1			T3	1		T5	1		T22	1
valid_sources[0x5c]	1962	1			T20	1		T141	1		T114	2
valid_sources[0x5d]	2409	1			T26	1		T38	1		T114	8
valid_sources[0x5e]	1877	1			T10	1		T15	2		T225	1
valid_sources[0x5f]	1944	1			T39	1		T38	1		T88	5
valid_sources[0x60]	2075	1			T1	28		T10	1		T39	3
valid_sources[0x61]	2200	1			T10	1		T19	1		T38	1
valid_sources[0x62]	1400	1			T22	1		T38	3		T141	1
valid_sources[0x63]	2026	1			T15	1		T26	1		T88	4
valid_sources[0x64]	1786	1			T3	1		T10	3		T27	1
valid_sources[0x65]	2576	1			T27	3		T39	2		T40	1
valid_sources[0x66]	1665	1			T10	2		T19	2		T39	2
valid_sources[0x67]	2154	1			T3	1		T66	2		T19	1
valid_sources[0x68]	1598	1			T3	1		T39	7		T26	1
valid_sources[0x69]	2006	1			T3	4		T10	1		T27	1
valid_sources[0x6a]	1904	1			T23	2		T27	1		T15	1
valid_sources[0x6b]	1370	1			T10	1		T66	1		T39	1
valid_sources[0x6c]	1913	1			T10	1		T27	1		T41	1
valid_sources[0x6d]	1971	1			T27	1		T66	1		T19	1
valid_sources[0x6e]	1813	1			T10	1		T38	1		T89	36
valid_sources[0x6f]	1951	1			T2	4		T10	1		T19	1
valid_sources[0x70]	2335	1			T5	1		T10	2		T39	1
valid_sources[0x71]	1599	1			T38	1		T141	1		T114	1
valid_sources[0x72]	2123	1			T3	1		T27	1		T39	2
valid_sources[0x73]	2046	1			T2	1		T22	2		T27	1
valid_sources[0x74]	2564	1			T3	1		T27	1		T15	1
valid_sources[0x75]	1689	1			T3	3		T15	1		T19	1
valid_sources[0x76]	3174	1			T10	1		T27	2		T66	1
valid_sources[0x77]	2111	1			T27	1		T39	1		T41	4
valid_sources[0x78]	1905	1			T3	2		T10	2		T19	1
valid_sources[0x79]	1964	1			T19	2		T39	2		T20	5
valid_sources[0x7a]	2052	1			T4	5		T70	2		T66	1
valid_sources[0x7b]	2021	1			T10	2		T70	1		T15	1
valid_sources[0x7c]	2136	1			T27	1		T15	1		T39	3
valid_sources[0x7d]	1944	1			T39	3		T26	1		T141	1
valid_sources[0x7e]	1541	1			T3	1		T22	1		T19	1
valid_sources[0x7f]	1811	1			T10	1		T19	1		T18	183
valid_sources[0x80]	2388	1			T3	1		T70	2		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91344

1

T1

5

T2

5

T3

11

values[0x0]

all_enables

biggest_size

124170

1

T1

2

T2

2

T3

4

values[0x1]

all_enables

biggest_size

122349

1

T1

2

T2

2

T3

2