Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 1797 1 T9 8 T11 4 T27 2
non_zero_bins[1] 1240 1 T11 3 T27 1 T19 4
zero 6289 1 T1 3 T2 3 T3 3



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 310 1 T39 1 T114 1 T143 1
uni 2225 1 T1 1 T2 1 T3 1
gen 3186 1 T1 1 T2 1 T3 1
res 644 1 T9 3 T11 2 T27 1
ins 2961 1 T1 1 T2 1 T3 1



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 5973 1 T1 2 T2 2 T3 2
mubi_true 3353 1 T1 1 T2 1 T3 1



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 38 1 T15 1 T86 1 T140 1
pass 9288 1 T1 3 T2 3 T3 3



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 80 1 T114 1 T131 1 T274 1
upd non_zero_bins[0] pass mubi_true 64 1 T143 1 T131 1 T309 1
upd non_zero_bins[1] pass mubi_false 53 1 T122 1 T56 1 T35 2
upd non_zero_bins[1] pass mubi_true 52 1 T39 1 T80 1 T35 3
upd zero pass mubi_false 30 1 T129 1 T35 2 T310 1
upd zero pass mubi_true 31 1 T54 1 T116 1 T309 1
uni zero pass mubi_false 1661 1 T11 1 T23 1 T27 1
uni zero pass mubi_true 564 1 T1 1 T2 1 T3 1
gen non_zero_bins[0] pass mubi_false 366 1 T9 3 T11 3 T39 1
gen non_zero_bins[0] pass mubi_true 340 1 T11 1 T49 4 T114 2
gen non_zero_bins[1] pass mubi_false 263 1 T27 1 T20 4 T114 1
gen non_zero_bins[1] pass mubi_true 239 1 T19 3 T38 4 T50 1
gen zero fail mubi_false 32 1 T15 1 T86 1 T140 1
gen zero pass mubi_false 1239 1 T1 1 T2 1 T3 1
gen zero pass mubi_true 707 1 T21 2 T10 2 T15 2
res non_zero_bins[0] pass mubi_false 167 1 T27 1 T19 3 T38 1
res non_zero_bins[0] pass mubi_true 143 1 T9 3 T38 3 T45 3
res non_zero_bins[1] pass mubi_false 89 1 T11 2 T129 1 T184 1
res non_zero_bins[1] pass mubi_true 90 1 T20 2 T125 1 T116 1
res zero fail mubi_false 6 1 T139 1 T191 1 T192 1
res zero pass mubi_false 91 1 T8 1 T53 1 T77 1
res zero pass mubi_true 58 1 T118 1 T309 1 T102 3
ins non_zero_bins[0] pass mubi_false 321 1 T9 1 T27 1 T39 3
ins non_zero_bins[0] pass mubi_true 316 1 T9 1 T114 2 T50 1
ins non_zero_bins[1] pass mubi_false 207 1 T11 1 T39 2 T38 1
ins non_zero_bins[1] pass mubi_true 247 1 T19 1 T20 1 T114 3
ins zero pass mubi_false 1368 1 T1 1 T2 1 T3 1
ins zero pass mubi_true 502 1 T10 1 T15 1 T26 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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