Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T25,T223,T224
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T21,T24,T38
DataWait->Error	99	Covered	T6,T7,T144
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T28,T16,T40

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	81419051	1072467	0	0
FpvSecCmErrorStEscalate_A	81419051	1080664	0	0
u_state_regs_A	81384694	80071158	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81419051	1072467	0	0
T5	9905	4585	0	0
T6	0	4550	0	0
T7	0	1897	0	0
T10	18354	0	0	0
T11	45556	0	0	0
T16	181335	79534	0	0
T17	0	52535	0	0
T18	0	100506	0	0
T22	7119	0	0	0
T23	13762	0	0	0
T24	7504	0	0	0
T27	17262	0	0	0
T28	6958	2715	0	0
T40	0	7706	0	0
T70	11137	0	0	0
T71	0	2750	0	0
T72	0	7994	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81419051	1080664	0	0
T5	9905	4592	0	0
T6	0	4557	0	0
T7	0	1904	0	0
T10	18354	0	0	0
T11	45556	0	0	0
T16	181335	80444	0	0
T17	0	53445	0	0
T18	0	102326	0	0
T22	7119	0	0	0
T23	13762	0	0	0
T24	7504	0	0	0
T27	17262	0	0	0
T28	6958	2722	0	0
T40	0	7713	0	0
T70	11137	0	0	0
T71	0	2757	0	0
T72	0	8001	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81384694	80071158	0	0
T1	7420	6979	0	0
T2	5852	5348	0	0
T3	14847	13720	0	0
T4	15075	13829	0	0
T5	9692	8712	0	0
T9	7903	7287	0	0
T10	18354	17878	0	0
T11	45556	45101	0	0
T21	5264	4627	0	0
T22	7119	6594	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T11 T45 T43 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T11 T45 T43 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T11 T45 T43 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T11 T45 T43 
80         1/1                    state_d = AckPls;
           Tests:       T11 T45 T43 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T11 T45 T43 
85         1/1                  state_d = Idle;
           Tests:       T11 T45 T43 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T45,T43
DataWait	75	Covered	T11,T45,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T11,T45,T43
DataWait->AckPls	80	Covered	T11,T45,T43
DataWait->Disabled	107	Covered	T77
DataWait->Error	99	Covered	T144,T138,T226
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T11,T45,T43
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T11,T45,T43
Idle	-	1	0	-	Covered	T11,T45,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T11,T45,T43
DataWait	-	-	-	0	Covered	T11,T45,T43
AckPls	-	-	-	-	Covered	T11,T45,T43
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	153531	0	0
FpvSecCmErrorStEscalate_A	11631293	154702	0	0
u_state_regs_A	11631293	11443645	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	153531	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	395	0	0
T40	0	1108	0	0
T70	1591	0	0	0
T71	0	400	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	154702	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	396	0	0
T40	0	1109	0	0
T70	1591	0	0	0
T71	0	401	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T21 T11 T19 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T21 T11 T19 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T21 T11 T19 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T21 T11 T19 
80         1/1                    state_d = AckPls;
           Tests:       T21 T11 T19 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T21 T11 T19 
85         1/1                  state_d = Idle;
           Tests:       T21 T11 T19 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T11,T19
DataWait	75	Covered	T21,T11,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T11,T19
DataWait->AckPls	80	Covered	T21,T11,T19
DataWait->Disabled	107	Covered	T21,T82,T206
DataWait->Error	99	Covered	T199,T154,T227
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T21,T11,T19
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T11,T19
Idle	-	1	0	-	Covered	T21,T11,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T11,T19
DataWait	-	-	-	0	Covered	T21,T11,T19
AckPls	-	-	-	-	Covered	T21,T11,T19
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	153531	0	0
FpvSecCmErrorStEscalate_A	11631293	154702	0	0
u_state_regs_A	11631293	11443645	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	153531	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	395	0	0
T40	0	1108	0	0
T70	1591	0	0	0
T71	0	400	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	154702	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	396	0	0
T40	0	1109	0	0
T70	1591	0	0	0
T71	0	401	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T9 T4 T5 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T9 T4 T20 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T9 T4 T5 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T9 T4 T20 
80         1/1                    state_d = AckPls;
           Tests:       T9 T4 T20 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T9 T4 T20 
85         1/1                  state_d = Idle;
           Tests:       T9 T4 T20 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T4,T20
DataWait	75	Covered	T9,T4,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T4,T20
DataWait->AckPls	80	Covered	T9,T4,T20
DataWait->Disabled	107	Covered	T185,T228
DataWait->Error	99	Covered	T151,T229,T216
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T4,T20
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T4,T20
Idle	-	1	0	-	Covered	T9,T4,T5
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T4,T20
DataWait	-	-	-	0	Covered	T9,T20,T59
AckPls	-	-	-	-	Covered	T9,T4,T20
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	153531	0	0
FpvSecCmErrorStEscalate_A	11631293	154702	0	0
u_state_regs_A	11631293	11443645	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	153531	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	395	0	0
T40	0	1108	0	0
T70	1591	0	0	0
T71	0	400	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	154702	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	396	0	0
T40	0	1109	0	0
T70	1591	0	0	0
T71	0	401	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T223
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T24,T38,T184
DataWait->Error	99	Covered	T7,T230,T231
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T16,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T28,T16,T40

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	151281	0	0
FpvSecCmErrorStEscalate_A	11631293	152452	0	0
u_state_regs_A	11596936	11409288	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	151281	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	345	0	0
T40	0	1058	0	0
T70	1591	0	0	0
T71	0	350	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	152452	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	346	0	0
T40	0	1059	0	0
T70	1591	0	0	0
T71	0	351	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11596936	11409288	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2097	1919	0	0
T5	1202	1062	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T11 T27 T28 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T11 T27 T28 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T11 T27 T28 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T11 T27 T28 
80         1/1                    state_d = AckPls;
           Tests:       T11 T27 T28 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T11 T27 T28 
85         1/1                  state_d = Idle;
           Tests:       T11 T27 T28 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T11,T27,T28
DataWait	75	Covered	T11,T27,T28
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T232
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T11,T27,T28
DataWait->AckPls	80	Covered	T11,T27,T28
DataWait->Disabled	107	Covered	T74,T156,T233
DataWait->Error	99	Covered	T6,T135,T221
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T11,T27,T28
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T11,T27,T28
Idle	-	1	0	-	Covered	T11,T27,T28
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T11,T27,T28
DataWait	-	-	-	0	Covered	T11,T27,T6
AckPls	-	-	-	-	Covered	T11,T27,T28
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	153531	0	0
FpvSecCmErrorStEscalate_A	11631293	154702	0	0
u_state_regs_A	11631293	11443645	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	153531	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	395	0	0
T40	0	1108	0	0
T70	1591	0	0	0
T71	0	400	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	154702	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	396	0	0
T40	0	1109	0	0
T70	1591	0	0	0
T71	0	401	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T20 T38 T51 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T20 T38 T51 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T20 T38 T51 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T20 T38 T51 
80         1/1                    state_d = AckPls;
           Tests:       T20 T38 T51 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T20 T38 T51 
85         1/1                  state_d = Idle;
           Tests:       T20 T38 T51 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T38,T51
DataWait	75	Covered	T20,T38,T51
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T224
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T38,T51
DataWait->AckPls	80	Covered	T20,T38,T51
DataWait->Disabled	107	Covered	T51,T90,T234
DataWait->Error	99	Covered	T193,T235,T169
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T38,T51
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T38,T51
Idle	-	1	0	-	Covered	T20,T38,T51
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T38,T51
DataWait	-	-	-	0	Covered	T20,T38,T51
AckPls	-	-	-	-	Covered	T20,T38,T51
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	153531	0	0
FpvSecCmErrorStEscalate_A	11631293	154702	0	0
u_state_regs_A	11631293	11443645	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	153531	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	395	0	0
T40	0	1108	0	0
T70	1591	0	0	0
T71	0	400	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	154702	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	396	0	0
T40	0	1109	0	0
T70	1591	0	0	0
T71	0	401	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T25 T54 T55 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T25 T54 T55 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T25 T54 T55 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T25 T54 T55 
80         1/1                    state_d = AckPls;
           Tests:       T25 T54 T55 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T25 T54 T55 
85         1/1                  state_d = Idle;
           Tests:       T25 T54 T55 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T28 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T28 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T28 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T28 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T28 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T9 T4 T21 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T9 T4 T21 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T9 T4 T21 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T9 T4 T21 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T4,T21

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T54,T55
DataWait	75	Covered	T25,T54,T55
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T28,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T25
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T54,T55
DataWait->AckPls	80	Covered	T25,T54,T55
DataWait->Disabled	107	Covered	T96,T236,T237
DataWait->Error	99	Covered	T167,T222
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T19,T225,T87
EndPointClear->Error	99	Covered	T16,T17,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T54,T55
Idle->Disabled	107	Covered	T3,T9,T4
Idle->Error	99	Covered	T5,T28,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T54,T55
Idle	-	1	0	-	Covered	T25,T54,T55
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T54,T55
DataWait	-	-	-	0	Covered	T25,T54,T56
AckPls	-	-	-	-	Covered	T25,T54,T55
Error	-	-	-	-	Covered	T5,T28,T16
default	-	-	-	-	Covered	T16,T17,T18

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T28,T16
0	1	Covered	T9,T4,T21
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	11631293	153531	0	0
FpvSecCmErrorStEscalate_A	11631293	154702	0	0
u_state_regs_A	11631293	11443645	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	153531	0	0
T5	1415	655	0	0
T6	0	650	0	0
T7	0	271	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11362	0	0
T17	0	7505	0	0
T18	0	14358	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	395	0	0
T40	0	1108	0	0
T70	1591	0	0	0
T71	0	400	0	0
T72	0	1142	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	154702	0	0
T5	1415	656	0	0
T6	0	651	0	0
T7	0	272	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T16	25905	11492	0	0
T17	0	7635	0	0
T18	0	14618	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	396	0	0
T40	0	1109	0	0
T70	1591	0	0	0
T71	0	401	0	0
T72	0	1143	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	11443645	0	0
T1	1060	997	0	0
T2	836	764	0	0
T3	2121	1960	0	0
T4	2163	1985	0	0
T5	1415	1275	0	0
T9	1129	1041	0	0
T10	2622	2554	0	0
T11	6508	6443	0	0
T21	752	661	0	0
T22	1017	942	0	0