Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[4].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[5].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[6].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[7].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[8].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[9].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[10].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[11].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[12].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[13].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[14].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[16].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[17].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[18].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[19].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_prim_mubi4_sync_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%