Unified Coverage Report :: Module :: prim_packer_fifo

Module : prim_packer_fifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	95.24			85.71	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	95.24			85.71	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.24	100.00	90.74			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.24	100.00

tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.24	95.24

tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T4,T10
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T15,T19
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T47,T48
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	93050344	9259247	0	7584
ValidOPairedWithReadyI_A	93050344	9259247	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93050344	9259247	0	7584
T1	1060	870	0	1
T2	836	535	0	1
T3	2121	1285	0	1
T4	2163	0	0	1
T5	2830	0	0	2
T6	5718	0	0	2
T7	1112	0	0	1
T9	1129	0	0	1
T10	5244	1250	0	2
T11	26032	9046	0	4
T12	0	1890	0	0
T15	6244	1563	0	2
T16	77715	0	0	3
T20	3651	0	0	1
T21	1504	0	0	2
T22	4068	0	0	4
T23	5898	1442	0	3
T24	2144	857	0	2
T27	7398	2597	0	3
T28	2982	402	0	3
T40	2111	0	0	1
T42	0	255	0	0
T43	0	867	0	0
T45	0	1159	0	0
T49	0	6235	0	0
T53	0	931	0	0
T54	0	1027	0	0
T66	0	1376	0	0
T70	4773	1156	0	3
T73	0	881	0	0
T74	0	776	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93050344	9259247	0	0
T1	1060	870	0	0
T2	836	535	0	0
T3	2121	1285	0	0
T4	2163	0	0	0
T5	2830	0	0	0
T6	5718	0	0	0
T7	1112	0	0	0
T9	1129	0	0	0
T10	5244	1250	0	0
T11	26032	9046	0	0
T12	0	1890	0	0
T15	6244	1563	0	0
T16	77715	0	0	0
T20	3651	0	0	0
T21	1504	0	0	0
T22	4068	0	0	0
T23	5898	1442	0	0
T24	2144	857	0	0
T27	7398	2597	0	0
T28	2982	402	0	0
T40	2111	0	0	0
T42	0	255	0	0
T43	0	867	0	0
T45	0	1159	0	0
T49	0	6235	0	0
T53	0	931	0	0
T54	0	1027	0	0
T66	0	1376	0	0
T70	4773	1156	0	0
T73	0	881	0	0
T74	0	776	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T4,T10
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T15,T19
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
Branches		14	12	85.71
TERNARY	142	4	3	75.00
TERNARY	147	3	2	66.67
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	90510	0	948
ValidOPairedWithReadyI_A	11631293	90510	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	90510	0	948
T4	2163	80	0	1
T5	1415	0	0	1
T9	1129	490	0	1
T10	2622	67	0	1
T11	6508	1001	0	1
T15	0	108	0	0
T19	0	351	0	0
T20	0	139	0	0
T21	752	0	0	1
T22	1017	0	0	1
T23	1966	0	0	1
T26	0	62	0	0
T27	2466	0	0	1
T28	0	55	0	0
T40	0	41	0	0
T70	1591	0	0	1

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	90510	0	0
T4	2163	80	0	0
T5	1415	0	0	0
T9	1129	490	0	0
T10	2622	67	0	0
T11	6508	1001	0	0
T15	0	108	0	0
T19	0	351	0	0
T20	0	139	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T26	0	62	0	0
T27	2466	0	0	0
T28	0	55	0	0
T40	0	41	0	0
T70	1591	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T196,T238
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	8032677	0	948
ValidOPairedWithReadyI_A	11631293	8032677	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	8032677	0	948
T1	1060	870	0	1
T2	836	535	0	1
T3	2121	1285	0	1
T4	2163	0	0	1
T5	1415	0	0	1
T9	1129	0	0	1
T10	2622	1250	0	1
T11	6508	0	0	1
T15	0	1563	0	0
T21	752	0	0	1
T22	1017	0	0	1
T23	0	1442	0	0
T24	0	857	0	0
T27	0	1301	0	0
T66	0	1376	0	0
T70	0	1156	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	8032677	0	0
T1	1060	870	0	0
T2	836	535	0	0
T3	2121	1285	0	0
T4	2163	0	0	0
T5	1415	0	0	0
T9	1129	0	0	0
T10	2622	1250	0	0
T11	6508	0	0	0
T15	0	1563	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	0	1442	0	0
T24	0	857	0	0
T27	0	1301	0	0
T66	0	1376	0	0
T70	0	1156	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T27,T49

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T27,T49
1	0	Covered	T11,T27,T28
1	1	Covered	T11,T27,T49

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T27,T49

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T11,T27,T28

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T27,T28
1	1	Covered	T11,T27,T28

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T27,T28

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T27,T28

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T27,T28

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T27,T28

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T27,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T239,T232,T240
1	1	Covered	T11,T27,T28

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T11,T27,T28
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T27,T28
0	0	1	Covered	T11,T27,T28
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T27,T28
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T27,T28
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	257541	0	948
ValidOPairedWithReadyI_A	11631293	257541	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	257541	0	948
T6	2859	0	0	1
T11	6508	3043	0	1
T12	0	968	0	0
T15	3122	0	0	1
T16	25905	0	0	1
T22	1017	0	0	1
T23	1966	0	0	1
T24	1072	0	0	1
T27	2466	1296	0	1
T28	994	402	0	1
T42	0	255	0	0
T49	0	6235	0	0
T53	0	931	0	0
T54	0	1027	0	0
T70	1591	0	0	1
T73	0	881	0	0
T74	0	776	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	257541	0	0
T6	2859	0	0	0
T11	6508	3043	0	0
T12	0	968	0	0
T15	3122	0	0	0
T16	25905	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	1296	0	0
T28	994	402	0	0
T42	0	255	0	0
T49	0	6235	0	0
T53	0	931	0	0
T54	0	1027	0	0
T70	1591	0	0	0
T73	0	881	0	0
T74	0	776	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T45,T43

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T45,T43
1	0	Covered	T11,T45,T43
1	1	Covered	T11,T45,T43

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T45,T43

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T11,T45,T43

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T45,T43
1	1	Covered	T11,T45,T43

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T45,T43

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T45,T43

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T45,T43

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T45,T43

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T45,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T48,T195
1	1	Covered	T11,T45,T43

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T11,T45,T43
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T45,T43
0	0	1	Covered	T11,T45,T43
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T45,T43
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T45,T43
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	211439	0	948
ValidOPairedWithReadyI_A	11631293	211439	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	211439	0	948
T6	2859	0	0	1
T11	6508	6003	0	1
T12	0	922	0	0
T15	3122	0	0	1
T16	25905	0	0	1
T22	1017	0	0	1
T23	1966	0	0	1
T24	1072	0	0	1
T27	2466	0	0	1
T28	994	0	0	1
T43	0	867	0	0
T44	0	1240	0	0
T45	0	1159	0	0
T46	0	1113	0	0
T47	0	54	0	0
T48	0	79	0	0
T70	1591	0	0	1
T77	0	1035	0	0
T78	0	1212	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	211439	0	0
T6	2859	0	0	0
T11	6508	6003	0	0
T12	0	922	0	0
T15	3122	0	0	0
T16	25905	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T24	1072	0	0	0
T27	2466	0	0	0
T28	994	0	0	0
T43	0	867	0	0
T44	0	1240	0	0
T45	0	1159	0	0
T46	0	1113	0	0
T47	0	54	0	0
T48	0	79	0	0
T70	1591	0	0	0
T77	0	1035	0	0
T78	0	1212	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T19,T49

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T19,T49
1	0	Covered	T21,T11,T19
1	1	Covered	T11,T19,T49

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T19,T49

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T11,T19

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T21,T11,T19
1	1	Covered	T21,T11,T19

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T11,T19

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T11,T19

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T11,T19

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T11,T19

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T11,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T139,T219
1	1	Covered	T21,T11,T19

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T21,T11,T19
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T21,T11,T19
0	0	1	Covered	T21,T11,T19
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T11,T19
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T11,T19
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	195426	0	948
ValidOPairedWithReadyI_A	11631293	195426	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	195426	0	948
T5	1415	0	0	1
T10	2622	0	0	1
T11	6508	5984	0	1
T16	25905	0	0	1
T19	0	524	0	0
T21	752	545	0	1
T22	1017	0	0	1
T23	1966	0	0	1
T27	2466	0	0	1
T28	994	0	0	1
T44	0	1229	0	0
T49	0	2964	0	0
T50	0	1239	0	0
T61	0	384	0	0
T70	1591	0	0	1
T77	0	1010	0	0
T81	0	1311	0	0
T82	0	1150	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	195426	0	0
T5	1415	0	0	0
T10	2622	0	0	0
T11	6508	5984	0	0
T16	25905	0	0	0
T19	0	524	0	0
T21	752	545	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T28	994	0	0	0
T44	0	1229	0	0
T49	0	2964	0	0
T50	0	1239	0	0
T61	0	384	0	0
T70	1591	0	0	0
T77	0	1010	0	0
T81	0	1311	0	0
T82	0	1150	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T38,T51

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T38,T51
1	0	Covered	T20,T38,T51
1	1	Covered	T20,T38,T51

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T38,T51

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T20,T38,T51

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T20,T38,T51
1	1	Covered	T20,T38,T51

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T38,T51

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T38,T51

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T38,T51

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T38,T51

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T38,T51
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T53,T211
1	1	Covered	T20,T38,T51

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T20,T38,T51
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T20,T38,T51
0	0	1	Covered	T20,T38,T51
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T20,T38,T51
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T20,T38,T51
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	168566	0	948
ValidOPairedWithReadyI_A	11631293	168566	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	168566	0	948
T7	1112	0	0	1
T20	3651	2600	0	1
T25	847	0	0	1
T26	2786	0	0	1
T38	2638	708	0	1
T40	2111	0	0	1
T41	9192	0	0	1
T44	0	1218	0	0
T50	0	1215	0	0
T51	0	1106	0	0
T52	0	94	0	0
T59	0	813	0	0
T69	1818	0	0	1
T71	0	409	0	0
T86	0	1353	0	0
T87	0	571	0	0
T88	1780	0	0	1
T89	1951	0	0	1

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	168566	0	0
T7	1112	0	0	0
T20	3651	2600	0	0
T25	847	0	0	0
T26	2786	0	0	0
T38	2638	708	0	0
T40	2111	0	0	0
T41	9192	0	0	0
T44	0	1218	0	0
T50	0	1215	0	0
T51	0	1106	0	0
T52	0	94	0	0
T59	0	813	0	0
T69	1818	0	0	0
T71	0	409	0	0
T86	0	1353	0	0
T87	0	571	0	0
T88	1780	0	0	0
T89	1951	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T56,T58

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T54,T56,T58
1	0	Covered	T25,T54,T55
1	1	Covered	T54,T56,T58

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T54,T56,T58

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T54,T55

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T25,T54,T55
1	1	Covered	T25,T54,T55

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T54,T55

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T54,T55

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T54,T55

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T54,T55

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T57,T95
1	1	Covered	T25,T54,T55

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T25,T54,T55
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T25,T54,T55
0	0	1	Covered	T25,T54,T55
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T54,T55
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T25,T54,T55
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	161283	0	948
ValidOPairedWithReadyI_A	11631293	161283	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	161283	0	948
T17	26363	0	0	1
T25	847	650	0	1
T38	2638	0	0	1
T41	9192	0	0	1
T49	7006	0	0	1
T51	1305	0	0	1
T54	0	1189	0	0
T55	0	453	0	0
T56	0	2037	0	0
T57	0	129	0	0
T58	0	1018	0	0
T71	932	0	0	1
T72	1876	0	0	1
T88	1780	0	0	1
T89	1951	0	0	1
T93	0	613	0	0
T94	0	593	0	0
T95	0	70	0	0
T96	0	1066	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	161283	0	0
T17	26363	0	0	0
T25	847	650	0	0
T38	2638	0	0	0
T41	9192	0	0	0
T49	7006	0	0	0
T51	1305	0	0	0
T54	0	1189	0	0
T55	0	453	0	0
T56	0	2037	0	0
T57	0	129	0	0
T58	0	1018	0	0
T71	932	0	0	0
T72	1876	0	0	0
T88	1780	0	0	0
T89	1951	0	0	0
T93	0	613	0	0
T94	0	593	0	0
T95	0	70	0	0
T96	0	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T20,T59

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T20,T59
1	0	Covered	T9,T4,T20
1	1	Covered	T9,T20,T59

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T20,T59

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T20

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T4,T20
1	1	Covered	T9,T4,T20

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T4,T20

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T4,T20

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T4,T20

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T4,T20

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T9,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T241,T242
1	1	Covered	T9,T4,T20

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T9,T4,T20
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T4,T20
0	0	1	Covered	T9,T4,T20
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T4,T20
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T4,T20
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	11631293	141805	0	948
ValidOPairedWithReadyI_A	11631293	141805	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	141805	0	948
T4	2163	1067	0	1
T5	1415	0	0	1
T9	1129	649	0	1
T10	2622	0	0	1
T11	6508	0	0	1
T20	0	1458	0	0
T21	752	0	0	1
T22	1017	0	0	1
T23	1966	0	0	1
T27	2466	0	0	1
T54	0	1165	0	0
T59	0	549	0	0
T70	1591	0	0	1
T101	0	193	0	0
T102	0	910	0	0
T103	0	810	0	0
T104	0	870	0	0
T105	0	1247	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11631293	141805	0	0
T4	2163	1067	0	0
T5	1415	0	0	0
T9	1129	649	0	0
T10	2622	0	0	0
T11	6508	0	0	0
T20	0	1458	0	0
T21	752	0	0	0
T22	1017	0	0	0
T23	1966	0	0	0
T27	2466	0	0	0
T54	0	1165	0	0
T59	0	549	0	0
T70	1591	0	0	0
T101	0	193	0	0
T102	0	910	0	0
T103	0	810	0	0
T104	0	870	0	0
T105	0	1247	0	0