SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
83.33 | 83.33 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
edn_alert_cg | 83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_recov_alert_cg | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[csrng_ack_err] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[edn_enable_field_alert] | 43 | 1 | T11 | 1 | T32 | 1 | T127 | 1 | ||||
auto[boot_req_mode_field_alert] | 59 | 1 | T128 | 1 | T46 | 1 | T83 | 1 | ||||
auto[auto_req_mode_field_alert] | 60 | 1 | T50 | 1 | T59 | 1 | T129 | 1 | ||||
auto[cmd_fifo_rst_field_alert] | 38 | 1 | T18 | 1 | T90 | 1 | T88 | 1 | ||||
auto[edn_bus_cmp_alert] | 200 | 1 | T18 | 1 | T11 | 1 | T32 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |