Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
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Group : tb.dut.u_edn_cov_if::edn_endpoint_err_req_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_endpoint_err_req_cg 100.00 1 100 1 64 64




Group Instance : edn_endpoint_err_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_endpoint_err_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group Instance edn_endpoint_err_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
endpoint_cg 7 0 7 100.00 100 1 1 0


Summary for Variable endpoint_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for endpoint_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
range[0x0] 501 1 T17 59 T20 127 T21 128
range[0x1] 525 1 T17 67 T20 133 T21 140
range[0x2] 537 1 T17 72 T20 140 T21 125
range[0x3] 503 1 T17 54 T20 127 T21 127
range[0x4] 528 1 T17 71 T20 130 T21 124
range[0x5] 561 1 T17 76 T20 141 T21 140
range[0x6] 498 1 T17 64 T20 126 T21 129

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%