Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_error_cg

Group : tb.dut.u_edn_cov_if::edn_error_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.50	87.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_error_cg	87.50	1	100	1	64	64

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Group Instance : edn_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

---

Summary for Group Instance edn_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group Instance edn_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_error_test	8	1	7	87.50	100	1	1	0

Summary for Variable cp_error_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	1	7	87.50

Automatically Generated Bins for cp_error_test

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[EdnFifoReadErrTest]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[EdnSfifoRescmdErrTest]	24	1			T17	1		T20	6		T21	5
auto[EdnSfifoGencmdErrTest]	32	1			T17	2		T20	7		T21	9
auto[EdnAckSmErrTest]	1140	1			T5	1		T16	1		T7	1
auto[EdnMainSmErrTest]	1140	1			T5	1		T16	1		T7	1
auto[EdnCntrErrTest]	107	1			T16	1		T7	1		T17	10
auto[EdnFifoWriteErrTest]	1	1			T102	1		-	-		-	-
auto[EdnFifoStateErrTest]	55	1			T17	3		T20	13		T21	14