Group : tb.dut.u_edn_cov_if::edn_error_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_error_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
87.50 87.50 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_error_cg 87.50 1 100 1 64 64




Group Instance : edn_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance edn_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group Instance edn_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error_test 8 1 7 87.50 100 1 1 0


Summary for Variable cp_error_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 1 7 87.50


Automatically Generated Bins for cp_error_test

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[EdnFifoReadErrTest] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[EdnSfifoRescmdErrTest] 24 1 T17 1 T20 6 T21 5
auto[EdnSfifoGencmdErrTest] 32 1 T17 2 T20 7 T21 9
auto[EdnAckSmErrTest] 1140 1 T5 1 T16 1 T7 1
auto[EdnMainSmErrTest] 1140 1 T5 1 T16 1 T7 1
auto[EdnCntrErrTest] 107 1 T16 1 T7 1 T17 10
auto[EdnFifoWriteErrTest] 1 1 T102 1 - - - -
auto[EdnFifoStateErrTest] 55 1 T17 3 T20 13 T21 14

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%