Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261426

1

T1

9

T2

9

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	172000	1			T1	19		T2	20		T3	311
values[0x0]	105854	1			T1	5		T2	4		T3	13
values[0x1]	117713	1			T1	2		T2	6		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	90586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

304981

1

T1

16

T2

16

T3

127

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1250	1			T2	1		T3	4		T18	5
valid_sources[0x01]	1738	1			T2	1		T17	3		T15	1
valid_sources[0x02]	1368	1			T31	3		T11	1		T17	2
valid_sources[0x03]	1242	1			T18	2		T19	1		T41	3
valid_sources[0x04]	1433	1			T17	5		T15	5		T65	1
valid_sources[0x05]	1825	1			T11	2		T17	4		T41	1
valid_sources[0x06]	1764	1			T40	1		T17	3		T15	3
valid_sources[0x07]	1565	1			T40	1		T17	2		T33	1
valid_sources[0x08]	1528	1			T18	3		T33	1		T41	1
valid_sources[0x09]	2082	1			T3	14		T40	2		T65	2
valid_sources[0x0a]	1069	1			T3	1		T40	1		T19	1
valid_sources[0x0b]	1126	1			T2	1		T4	1		T11	1
valid_sources[0x0c]	1610	1			T40	2		T11	2		T65	1
valid_sources[0x0d]	1505	1			T3	2		T4	3		T40	1
valid_sources[0x0e]	1422	1			T3	1		T19	1		T17	3
valid_sources[0x0f]	1693	1			T3	1		T31	3		T11	1
valid_sources[0x10]	1385	1			T2	1		T3	4		T4	4
valid_sources[0x11]	1480	1			T17	1		T32	1		T53	2
valid_sources[0x12]	1503	1			T40	2		T17	3		T32	2
valid_sources[0x13]	1407	1			T18	3		T53	1		T61	8
valid_sources[0x14]	1537	1			T3	11		T40	1		T17	1
valid_sources[0x15]	1301	1			T2	2		T3	3		T40	2
valid_sources[0x16]	1975	1			T41	3		T61	2		T312	1
valid_sources[0x17]	1334	1			T18	1		T33	1		T32	1
valid_sources[0x18]	1412	1			T18	1		T41	1		T53	1
valid_sources[0x19]	1829	1			T17	4		T33	1		T41	3
valid_sources[0x1a]	1335	1			T2	1		T18	1		T31	5
valid_sources[0x1b]	1612	1			T17	6		T15	1		T41	1
valid_sources[0x1c]	1147	1			T3	7		T17	5		T32	1
valid_sources[0x1d]	1529	1			T17	2		T41	1		T8	1
valid_sources[0x1e]	1578	1			T4	2		T11	2		T61	4
valid_sources[0x1f]	1531	1			T29	1		T41	1		T61	10
valid_sources[0x20]	1659	1			T17	2		T41	2		T32	1
valid_sources[0x21]	1571	1			T18	1		T65	1		T57	4
valid_sources[0x22]	1778	1			T17	1		T41	1		T32	1
valid_sources[0x23]	1863	1			T5	4		T17	5		T15	2
valid_sources[0x24]	1244	1			T17	2		T20	10		T21	14
valid_sources[0x25]	1459	1			T3	1		T19	1		T65	1
valid_sources[0x26]	1328	1			T3	3		T17	1		T41	1
valid_sources[0x27]	1127	1			T5	3		T40	1		T17	3
valid_sources[0x28]	1365	1			T29	1		T17	1		T67	6
valid_sources[0x29]	1272	1			T40	2		T53	3		T312	1
valid_sources[0x2a]	1504	1			T2	1		T40	1		T15	1
valid_sources[0x2b]	1175	1			T2	1		T15	1		T41	1
valid_sources[0x2c]	1166	1			T3	1		T19	1		T61	2
valid_sources[0x2d]	1766	1			T40	1		T19	1		T11	1
valid_sources[0x2e]	1241	1			T4	1		T18	3		T19	1
valid_sources[0x2f]	1482	1			T18	3		T15	1		T33	3
valid_sources[0x30]	1343	1			T29	2		T17	4		T33	1
valid_sources[0x31]	1263	1			T3	7		T18	1		T5	2
valid_sources[0x32]	1469	1			T40	1		T11	2		T17	1
valid_sources[0x33]	1606	1			T15	2		T41	1		T32	1
valid_sources[0x34]	1284	1			T2	1		T18	3		T19	1
valid_sources[0x35]	1251	1			T17	1		T41	1		T70	1
valid_sources[0x36]	1374	1			T17	1		T65	1		T32	1
valid_sources[0x37]	1134	1			T40	1		T17	1		T15	5
valid_sources[0x38]	1670	1			T3	12		T4	1		T17	3
valid_sources[0x39]	1313	1			T2	1		T40	1		T17	3
valid_sources[0x3a]	1548	1			T3	4		T18	1		T17	1
valid_sources[0x3b]	1442	1			T3	1		T18	6		T40	1
valid_sources[0x3c]	1553	1			T19	1		T15	3		T53	5
valid_sources[0x3d]	1749	1			T67	5		T33	1		T53	1
valid_sources[0x3e]	1609	1			T11	1		T17	5		T65	2
valid_sources[0x3f]	1775	1			T4	1		T17	5		T15	1
valid_sources[0x40]	1538	1			T65	1		T41	1		T53	1
valid_sources[0x41]	1369	1			T3	3		T11	1		T17	6
valid_sources[0x42]	1423	1			T31	3		T40	2		T11	1
valid_sources[0x43]	1395	1			T17	1		T70	2		T61	1
valid_sources[0x44]	1957	1			T40	1		T8	1		T20	3
valid_sources[0x45]	1830	1			T2	1		T18	1		T17	4
valid_sources[0x46]	1196	1			T3	1		T40	3		T17	2
valid_sources[0x47]	1448	1			T17	5		T65	1		T32	1
valid_sources[0x48]	1718	1			T3	1		T4	1		T40	2
valid_sources[0x49]	1489	1			T3	6		T18	3		T17	1
valid_sources[0x4a]	1430	1			T11	1		T17	4		T66	8
valid_sources[0x4b]	1528	1			T5	4		T11	1		T53	1
valid_sources[0x4c]	1126	1			T18	2		T11	2		T61	1
valid_sources[0x4d]	1681	1			T19	1		T11	1		T17	1
valid_sources[0x4e]	2088	1			T2	1		T3	2		T4	2
valid_sources[0x4f]	1516	1			T17	7		T65	1		T41	2
valid_sources[0x50]	1284	1			T3	7		T29	1		T5	1
valid_sources[0x51]	1866	1			T2	1		T3	20		T11	1
valid_sources[0x52]	1216	1			T4	1		T31	1		T40	1
valid_sources[0x53]	2224	1			T17	2		T33	1		T32	2
valid_sources[0x54]	1492	1			T40	1		T17	1		T8	1
valid_sources[0x55]	1337	1			T29	1		T17	1		T15	1
valid_sources[0x56]	1341	1			T2	1		T17	2		T15	2
valid_sources[0x57]	1646	1			T3	1		T29	2		T16	4
valid_sources[0x58]	1178	1			T3	6		T40	1		T17	6
valid_sources[0x59]	1310	1			T18	1		T29	1		T17	2
valid_sources[0x5a]	1306	1			T40	1		T17	1		T65	1
valid_sources[0x5b]	1684	1			T40	1		T11	1		T17	2
valid_sources[0x5c]	1259	1			T4	1		T31	1		T40	1
valid_sources[0x5d]	1764	1			T3	15		T40	1		T19	1
valid_sources[0x5e]	1330	1			T17	1		T20	4		T21	4
valid_sources[0x5f]	1316	1			T18	1		T17	5		T15	3
valid_sources[0x60]	1124	1			T17	2		T56	2		T53	1
valid_sources[0x61]	1087	1			T3	8		T33	1		T53	1
valid_sources[0x62]	1657	1			T11	1		T17	3		T41	1
valid_sources[0x63]	1517	1			T29	2		T8	2		T61	7
valid_sources[0x64]	1738	1			T3	4		T18	1		T8	1
valid_sources[0x65]	2035	1			T1	26		T18	1		T40	1
valid_sources[0x66]	1843	1			T18	2		T17	4		T33	1
valid_sources[0x67]	2033	1			T3	1		T40	1		T17	1
valid_sources[0x68]	1700	1			T40	1		T11	2		T17	2
valid_sources[0x69]	1266	1			T4	2		T17	1		T32	1
valid_sources[0x6a]	1460	1			T3	8		T4	1		T40	1
valid_sources[0x6b]	1325	1			T18	1		T17	1		T65	1
valid_sources[0x6c]	2111	1			T4	4		T18	1		T17	3
valid_sources[0x6d]	1501	1			T11	1		T33	1		T41	2
valid_sources[0x6e]	1206	1			T2	1		T40	1		T41	1
valid_sources[0x6f]	1481	1			T17	2		T65	1		T41	2
valid_sources[0x70]	1511	1			T17	3		T41	3		T32	1
valid_sources[0x71]	1071	1			T40	1		T17	1		T58	1
valid_sources[0x72]	2248	1			T3	6		T17	1		T8	2
valid_sources[0x73]	1574	1			T40	1		T11	2		T17	3
valid_sources[0x74]	1013	1			T3	5		T28	4		T5	3
valid_sources[0x75]	1947	1			T3	1		T4	2		T40	2
valid_sources[0x76]	2227	1			T40	1		T17	3		T61	4
valid_sources[0x77]	1563	1			T17	1		T41	2		T68	3
valid_sources[0x78]	1465	1			T17	2		T65	1		T41	2
valid_sources[0x79]	2801	1			T17	2		T67	9		T50	1
valid_sources[0x7a]	1911	1			T3	2		T11	1		T41	1
valid_sources[0x7b]	1409	1			T31	4		T41	1		T61	1
valid_sources[0x7c]	1638	1			T11	2		T17	1		T33	1
valid_sources[0x7d]	1619	1			T2	1		T40	1		T33	1
valid_sources[0x7e]	2103	1			T40	1		T19	1		T11	1
valid_sources[0x7f]	1657	1			T3	2		T40	2		T60	220
valid_sources[0x80]	1324	1			T18	1		T31	4		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70741

1

T1

3

T2

3

T3

7

values[0x0]

all_enables

biggest_size

96211

1

T1

4

T2

3

T3

10

values[0x1]

all_enables

biggest_size

94474

1

T1

2

T2

3

T3

8