Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1718	1			T3	1		T6	6		T40	1
non_zero_bins[1]	1235	1			T3	1		T10	4		T6	11
zero	5569	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	268	1			T6	3		T40	1		T60	1
uni	1926	1			T1	1		T2	1		T3	1
gen	3022	1			T1	1		T2	1		T3	1
res	643	1			T3	1		T10	4		T6	1
ins	2663	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5302

1

T1

3

T2

2

T3

4

mubi_true

3220

1

T2

1

T18

3

T28

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

30

1

T32

1

T90

1

T297

1

pass

8492

1

T1

3

T2

3

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	71	1			T6	1		T42	1		T114	2
upd	non_zero_bins[0]	pass	mubi_true	66	1			T6	1		T60	1		T112	2
upd	non_zero_bins[1]	pass	mubi_false	30	1			T37	1		T298	1		T299	1
upd	non_zero_bins[1]	pass	mubi_true	51	1			T6	1		T40	1		T124	1
upd	zero	pass	mubi_false	23	1			T37	1		T250	1		T300	1
upd	zero	pass	mubi_true	27	1			T61	1		T124	1		T109	1
uni	zero	pass	mubi_false	1475	1			T1	1		T3	1		T30	1
uni	zero	pass	mubi_true	451	1			T2	1		T6	1		T66	1
gen	non_zero_bins[0]	pass	mubi_false	345	1			T3	1		T6	1		T40	1
gen	non_zero_bins[0]	pass	mubi_true	378	1			T124	2		T72	3		T109	1
gen	non_zero_bins[1]	pass	mubi_false	260	1			T10	3		T6	4		T60	1
gen	non_zero_bins[1]	pass	mubi_true	265	1			T6	1		T41	1		T61	1
gen	zero	fail	mubi_false	27	1			T32	1		T90	1		T297	1
gen	zero	pass	mubi_false	1075	1			T1	1		T2	1		T4	1
gen	zero	pass	mubi_true	672	1			T18	2		T5	1		T11	2
res	non_zero_bins[0]	pass	mubi_false	136	1			T60	1		T15	5		T57	1
res	non_zero_bins[0]	pass	mubi_true	141	1			T53	1		T22	2		T114	1
res	non_zero_bins[1]	pass	mubi_false	119	1			T6	1		T112	1		T122	1
res	non_zero_bins[1]	pass	mubi_true	88	1			T37	1		T80	1		T38	1
res	zero	fail	mubi_false	3	1			T169	1		T301	1		T302	1
res	zero	pass	mubi_false	90	1			T3	1		T11	1		T112	1
res	zero	pass	mubi_true	66	1			T10	4		T109	2		T119	3
ins	non_zero_bins[0]	pass	mubi_false	279	1			T6	2		T60	1		T15	1
ins	non_zero_bins[0]	pass	mubi_true	302	1			T6	1		T53	1		T61	3
ins	non_zero_bins[1]	pass	mubi_false	209	1			T3	1		T10	1		T6	2
ins	non_zero_bins[1]	pass	mubi_true	213	1			T6	2		T60	1		T15	1
ins	zero	pass	mubi_false	1160	1			T1	1		T2	1		T4	1
ins	zero	pass	mubi_true	500	1			T18	1		T28	2		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded