Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T91,T208
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T28,T22,T37
DataWait->Error	99	Covered	T16,T8,T58
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T5,T16,T17

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T5,T17,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	74268502	1088587	0	0
FpvSecCmErrorStEscalate_A	74268502	1096770	0	0
u_state_regs_A	74231220	72907618	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74268502	1088587	0	0
T5	16765	5018	0	0
T6	107632	0	0	0
T7	12768	5971	0	0
T8	0	7560	0	0
T11	17780	0	0	0
T16	13041	7714	0	0
T17	192717	75236	0	0
T19	16254	0	0	0
T20	0	151151	0	0
T21	0	99883	0	0
T31	10941	0	0	0
T40	23492	0	0	0
T56	6496	0	0	0
T58	0	1617	0	0
T71	0	7476	0	0
T207	0	2470	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74268502	1096770	0	0
T5	16765	5025	0	0
T6	107632	0	0	0
T7	12768	5978	0	0
T8	0	7567	0	0
T11	17780	0	0	0
T16	13041	7721	0	0
T17	192717	76146	0	0
T19	16254	0	0	0
T20	0	152971	0	0
T21	0	101703	0	0
T31	10941	0	0	0
T40	23492	0	0	0
T56	6496	0	0	0
T58	0	1624	0	0
T71	0	7483	0	0
T207	0	2477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74231220	72907618	0	0
T1	9870	9464	0	0
T2	10290	9912	0	0
T3	17234	16737	0	0
T4	7910	7007	0	0
T5	15563	14471	0	0
T10	21749	21280	0	0
T18	14161	13671	0	0
T28	5033	4333	0	0
T29	11361	10752	0	0
T30	12712	12068	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T4 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T4 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T4 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T4 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T4 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T4 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T4 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T22,T37,T38
DataWait->Error	99	Covered	T8,T58,T211
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T16,T17,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T1,T2,T30
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T5,T17,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	153541	0	0
FpvSecCmErrorStEscalate_A	10609786	154710	0	0
u_state_regs_A	10572504	10383418	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	153541	0	0
T5	2395	674	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	310	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	154710	0	0
T5	2395	675	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	311	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10572504	10383418	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1118	989	0	0
T5	1193	1037	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T18 T16 T11 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T18 T11 T41 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T18 T16 T11 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T18 T16 T11 
80         1/1                    state_d = AckPls;
           Tests:       T18 T11 T41 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T18 T11 T41 
85         1/1                  state_d = Idle;
           Tests:       T18 T11 T41 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T18,T11,T41
DataWait	75	Covered	T18,T16,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T18,T11,T41
DataWait->AckPls	80	Covered	T18,T11,T41
DataWait->Disabled	107	Covered	T73,T212,T213
DataWait->Error	99	Covered	T16,T176,T214
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T18,T16,T11
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T5,T17,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T18,T11,T41
Idle	-	1	0	-	Covered	T18,T16,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T18,T11,T41
DataWait	-	-	-	0	Covered	T16,T41,T53
AckPls	-	-	-	-	Covered	T18,T11,T41
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T17,T20,T21

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	155841	0	0
FpvSecCmErrorStEscalate_A	10609786	157010	0	0
u_state_regs_A	10609786	10420700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	155841	0	0
T5	2395	724	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	157010	0	0
T5	2395	725	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T3 T18 T40 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T3 T18 T40 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T3 T18 T40 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T3 T18 T40 
80         1/1                    state_d = AckPls;
           Tests:       T3 T18 T40 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T3 T18 T40 
85         1/1                  state_d = Idle;
           Tests:       T3 T18 T40 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T18,T40
DataWait	75	Covered	T3,T18,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T18,T40
DataWait->AckPls	80	Covered	T3,T18,T40
DataWait->Disabled	107	Covered	T79,T81,T215
DataWait->Error	99	Covered	T216,T196,T155
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T18,T40
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T5,T16,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T18,T40
Idle	-	1	0	-	Covered	T3,T18,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T18,T40
DataWait	-	-	-	0	Covered	T3,T18,T40
AckPls	-	-	-	-	Covered	T3,T18,T40
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T17,T20,T21

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	155841	0	0
FpvSecCmErrorStEscalate_A	10609786	157010	0	0
u_state_regs_A	10609786	10420700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	155841	0	0
T5	2395	724	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	157010	0	0
T5	2395	725	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T3 T10 T45 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T3 T10 T45 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T3 T10 T45 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T3 T10 T45 
80         1/1                    state_d = AckPls;
           Tests:       T3 T10 T45 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T3 T10 T45 
85         1/1                  state_d = Idle;
           Tests:       T3 T10 T45 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T10,T45
DataWait	75	Covered	T3,T10,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T10,T45
DataWait->AckPls	80	Covered	T3,T10,T45
DataWait->Disabled	107	Covered	T217,T218
DataWait->Error	99	Covered	T170,T219,T220
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T10,T45
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T5,T16,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T10,T45
Idle	-	1	0	-	Covered	T3,T10,T45
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T10,T45
DataWait	-	-	-	0	Covered	T3,T10,T45
AckPls	-	-	-	-	Covered	T3,T10,T45
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T17,T20,T21

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	155841	0	0
FpvSecCmErrorStEscalate_A	10609786	157010	0	0
u_state_regs_A	10609786	10420700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	155841	0	0
T5	2395	724	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	157010	0	0
T5	2395	725	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T3 T5 T56 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T3 T56 T57 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T3 T5 T56 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T3 T5 T56 
80         1/1                    state_d = AckPls;
           Tests:       T3 T56 T57 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T3 T56 T57 
85         1/1                  state_d = Idle;
           Tests:       T3 T56 T57 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T56,T57
DataWait	75	Covered	T3,T5,T56
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T56,T57
DataWait->AckPls	80	Covered	T3,T56,T57
DataWait->Disabled	107	Covered	T221,T222
DataWait->Error	99	Covered	T5,T223,T224
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T5,T56
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T16,T17,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T56,T57
Idle	-	1	0	-	Covered	T3,T5,T56
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T56,T57
DataWait	-	-	-	0	Covered	T3,T5,T56
AckPls	-	-	-	-	Covered	T3,T56,T57
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T17,T20,T21

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	155841	0	0
FpvSecCmErrorStEscalate_A	10609786	157010	0	0
u_state_regs_A	10609786	10420700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	155841	0	0
T5	2395	724	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	157010	0	0
T5	2395	725	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T3 T28 T40 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T3 T28 T40 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T3 T28 T40 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T3 T28 T40 
80         1/1                    state_d = AckPls;
           Tests:       T3 T28 T40 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T3 T28 T40 
85         1/1                  state_d = Idle;
           Tests:       T3 T28 T40 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T28,T40
DataWait	75	Covered	T3,T28,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T208
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T28,T40
DataWait->AckPls	80	Covered	T3,T28,T40
DataWait->Disabled	107	Covered	T28,T15,T86
DataWait->Error	99	Covered	T64,T225
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T28,T40
Idle->Disabled	107	Covered	T4,T18,T10
Idle->Error	99	Covered	T5,T16,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T28,T40
Idle	-	1	0	-	Covered	T3,T28,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T28,T40
DataWait	-	-	-	0	Covered	T3,T28,T40
AckPls	-	-	-	-	Covered	T3,T28,T40
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T17,T20,T21

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	155841	0	0
FpvSecCmErrorStEscalate_A	10609786	157010	0	0
u_state_regs_A	10609786	10420700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	155841	0	0
T5	2395	724	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	157010	0	0
T5	2395	725	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T3 T40 T53 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T3 T40 T53 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T3 T40 T53 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T3 T40 T53 
80         1/1                    state_d = AckPls;
           Tests:       T3 T40 T53 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T3 T40 T53 
85         1/1                  state_d = Idle;
           Tests:       T3 T40 T53 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T16 T7 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T16 T7 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T16 T7 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T16 T7 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T16 T7 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T4 T18 T28 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T4 T18 T28 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T4 T18 T28 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T4 T18 T28 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T40,T53
DataWait	75	Covered	T3,T40,T53
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T16,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T91
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T40,T53
DataWait->AckPls	80	Covered	T3,T40,T53
DataWait->Disabled	107	Covered	T53,T52,T23
DataWait->Error	99	Covered	T195,T205,T226
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T20,T21
EndPointClear->Disabled	107	Covered	T122,T209,T210
EndPointClear->Error	99	Covered	T7,T17,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T40,T53
Idle->Disabled	107	Covered	T4,T18,T28
Idle->Error	99	Covered	T5,T16,T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T40,T53
Idle	-	1	0	-	Covered	T3,T40,T53
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T40,T53
DataWait	-	-	-	0	Covered	T3,T40,T53
AckPls	-	-	-	-	Covered	T3,T40,T53
Error	-	-	-	-	Covered	T5,T16,T7
default	-	-	-	-	Covered	T17,T20,T21

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T16,T7
0	1	Covered	T4,T18,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10609786	155841	0	0
FpvSecCmErrorStEscalate_A	10609786	157010	0	0
u_state_regs_A	10609786	10420700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	155841	0	0
T5	2395	724	0	0
T6	15376	0	0	0
T7	1824	853	0	0
T8	0	1080	0	0
T11	2540	0	0	0
T16	1863	1102	0	0
T17	27531	10748	0	0
T19	2322	0	0	0
T20	0	21593	0	0
T21	0	14269	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	231	0	0
T71	0	1068	0	0
T207	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	157010	0	0
T5	2395	725	0	0
T6	15376	0	0	0
T7	1824	854	0	0
T8	0	1081	0	0
T11	2540	0	0	0
T16	1863	1103	0	0
T17	27531	10878	0	0
T19	2322	0	0	0
T20	0	21853	0	0
T21	0	14529	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T56	928	0	0	0
T58	0	232	0	0
T71	0	1069	0	0
T207	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	10420700	0	0
T1	1410	1352	0	0
T2	1470	1416	0	0
T3	2462	2391	0	0
T4	1132	1003	0	0
T5	2395	2239	0	0
T10	3107	3040	0	0
T18	2023	1953	0	0
T28	719	619	0	0
T29	1623	1536	0	0
T30	1816	1724	0	0