Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T18 T10 T5
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T18 T10 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T18 T10 T5
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T10,T19 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T18,T10,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T19,T35,T101 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T18,T10,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T33,T36 |
| 1 | 0 | 1 | Covered | T18,T10,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T10,T11,T15 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T10,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
20485196 |
1984483 |
0 |
0 |
| T5 |
342 |
0 |
0 |
0 |
| T6 |
30752 |
0 |
0 |
0 |
| T7 |
0 |
136 |
0 |
0 |
| T8 |
0 |
77 |
0 |
0 |
| T10 |
6214 |
3977 |
0 |
0 |
| T11 |
0 |
577 |
0 |
0 |
| T15 |
0 |
4245 |
0 |
0 |
| T18 |
4046 |
572 |
0 |
0 |
| T19 |
1168 |
0 |
0 |
0 |
| T22 |
0 |
2637 |
0 |
0 |
| T28 |
1438 |
0 |
0 |
0 |
| T29 |
3246 |
0 |
0 |
0 |
| T30 |
3632 |
0 |
0 |
0 |
| T31 |
3126 |
0 |
0 |
0 |
| T32 |
0 |
412 |
0 |
0 |
| T40 |
6712 |
0 |
0 |
0 |
| T53 |
0 |
1716 |
0 |
0 |
| T59 |
0 |
720 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
21219572 |
20841400 |
0 |
0 |
| T1 |
2820 |
2704 |
0 |
0 |
| T2 |
2940 |
2832 |
0 |
0 |
| T3 |
4924 |
4782 |
0 |
0 |
| T4 |
2264 |
2006 |
0 |
0 |
| T5 |
4790 |
4478 |
0 |
0 |
| T10 |
6214 |
6080 |
0 |
0 |
| T18 |
4046 |
3906 |
0 |
0 |
| T28 |
1438 |
1238 |
0 |
0 |
| T29 |
3246 |
3072 |
0 |
0 |
| T30 |
3632 |
3448 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
21219572 |
20841400 |
0 |
0 |
| T1 |
2820 |
2704 |
0 |
0 |
| T2 |
2940 |
2832 |
0 |
0 |
| T3 |
4924 |
4782 |
0 |
0 |
| T4 |
2264 |
2006 |
0 |
0 |
| T5 |
4790 |
4478 |
0 |
0 |
| T10 |
6214 |
6080 |
0 |
0 |
| T18 |
4046 |
3906 |
0 |
0 |
| T28 |
1438 |
1238 |
0 |
0 |
| T29 |
3246 |
3072 |
0 |
0 |
| T30 |
3632 |
3448 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
21219572 |
20841400 |
0 |
0 |
| T1 |
2820 |
2704 |
0 |
0 |
| T2 |
2940 |
2832 |
0 |
0 |
| T3 |
4924 |
4782 |
0 |
0 |
| T4 |
2264 |
2006 |
0 |
0 |
| T5 |
4790 |
4478 |
0 |
0 |
| T10 |
6214 |
6080 |
0 |
0 |
| T18 |
4046 |
3906 |
0 |
0 |
| T28 |
1438 |
1238 |
0 |
0 |
| T29 |
3246 |
3072 |
0 |
0 |
| T30 |
3632 |
3448 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
20835818 |
2081810 |
0 |
0 |
| T5 |
4790 |
3482 |
0 |
0 |
| T6 |
30752 |
0 |
0 |
0 |
| T7 |
0 |
1427 |
0 |
0 |
| T8 |
0 |
1590 |
0 |
0 |
| T10 |
6214 |
3977 |
0 |
0 |
| T11 |
0 |
577 |
0 |
0 |
| T15 |
0 |
4245 |
0 |
0 |
| T16 |
0 |
307 |
0 |
0 |
| T18 |
4046 |
572 |
0 |
0 |
| T19 |
4644 |
24 |
0 |
0 |
| T28 |
1438 |
0 |
0 |
0 |
| T29 |
3246 |
0 |
0 |
0 |
| T30 |
3632 |
0 |
0 |
0 |
| T31 |
3126 |
0 |
0 |
0 |
| T32 |
0 |
412 |
0 |
0 |
| T40 |
6712 |
0 |
0 |
0 |
| T53 |
0 |
846 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T18 T10 T5
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T18 T10 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T18 T10 T5
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T23,T26,T35 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T18,T10,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T35,T101,T102 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T18,T10,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T33,T36 |
| 1 | 0 | 1 | Covered | T18,T10,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T10,T11,T15 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T10,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10242598 |
986040 |
0 |
0 |
| T5 |
171 |
0 |
0 |
0 |
| T6 |
15376 |
0 |
0 |
0 |
| T7 |
0 |
36 |
0 |
0 |
| T8 |
0 |
37 |
0 |
0 |
| T10 |
3107 |
1969 |
0 |
0 |
| T11 |
0 |
290 |
0 |
0 |
| T15 |
0 |
2079 |
0 |
0 |
| T18 |
2023 |
257 |
0 |
0 |
| T19 |
584 |
0 |
0 |
0 |
| T22 |
0 |
1257 |
0 |
0 |
| T28 |
719 |
0 |
0 |
0 |
| T29 |
1623 |
0 |
0 |
0 |
| T30 |
1816 |
0 |
0 |
0 |
| T31 |
1563 |
0 |
0 |
0 |
| T32 |
0 |
195 |
0 |
0 |
| T40 |
3356 |
0 |
0 |
0 |
| T53 |
0 |
846 |
0 |
0 |
| T59 |
0 |
363 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10609786 |
10420700 |
0 |
0 |
| T1 |
1410 |
1352 |
0 |
0 |
| T2 |
1470 |
1416 |
0 |
0 |
| T3 |
2462 |
2391 |
0 |
0 |
| T4 |
1132 |
1003 |
0 |
0 |
| T5 |
2395 |
2239 |
0 |
0 |
| T10 |
3107 |
3040 |
0 |
0 |
| T18 |
2023 |
1953 |
0 |
0 |
| T28 |
719 |
619 |
0 |
0 |
| T29 |
1623 |
1536 |
0 |
0 |
| T30 |
1816 |
1724 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10609786 |
10420700 |
0 |
0 |
| T1 |
1410 |
1352 |
0 |
0 |
| T2 |
1470 |
1416 |
0 |
0 |
| T3 |
2462 |
2391 |
0 |
0 |
| T4 |
1132 |
1003 |
0 |
0 |
| T5 |
2395 |
2239 |
0 |
0 |
| T10 |
3107 |
3040 |
0 |
0 |
| T18 |
2023 |
1953 |
0 |
0 |
| T28 |
719 |
619 |
0 |
0 |
| T29 |
1623 |
1536 |
0 |
0 |
| T30 |
1816 |
1724 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10609786 |
10420700 |
0 |
0 |
| T1 |
1410 |
1352 |
0 |
0 |
| T2 |
1470 |
1416 |
0 |
0 |
| T3 |
2462 |
2391 |
0 |
0 |
| T4 |
1132 |
1003 |
0 |
0 |
| T5 |
2395 |
2239 |
0 |
0 |
| T10 |
3107 |
3040 |
0 |
0 |
| T18 |
2023 |
1953 |
0 |
0 |
| T28 |
719 |
619 |
0 |
0 |
| T29 |
1623 |
1536 |
0 |
0 |
| T30 |
1816 |
1724 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10417909 |
1034486 |
0 |
0 |
| T5 |
2395 |
1744 |
0 |
0 |
| T6 |
15376 |
0 |
0 |
0 |
| T7 |
0 |
652 |
0 |
0 |
| T8 |
0 |
784 |
0 |
0 |
| T10 |
3107 |
1969 |
0 |
0 |
| T11 |
0 |
290 |
0 |
0 |
| T15 |
0 |
2079 |
0 |
0 |
| T16 |
0 |
155 |
0 |
0 |
| T18 |
2023 |
257 |
0 |
0 |
| T19 |
2322 |
0 |
0 |
0 |
| T28 |
719 |
0 |
0 |
0 |
| T29 |
1623 |
0 |
0 |
0 |
| T30 |
1816 |
0 |
0 |
0 |
| T31 |
1563 |
0 |
0 |
0 |
| T32 |
0 |
195 |
0 |
0 |
| T40 |
3356 |
0 |
0 |
0 |
| T53 |
0 |
846 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T18 T10 T5
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T18 T10 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T18 T10 T5
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T10,T19 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T18,T10,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T19,T103 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T18,T10,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T104,T105,T106 |
| 1 | 0 | 1 | Covered | T18,T10,T5 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T10,T11,T15 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T18,T10,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10242598 |
998443 |
0 |
0 |
| T5 |
171 |
0 |
0 |
0 |
| T6 |
15376 |
0 |
0 |
0 |
| T7 |
0 |
100 |
0 |
0 |
| T8 |
0 |
40 |
0 |
0 |
| T10 |
3107 |
2008 |
0 |
0 |
| T11 |
0 |
287 |
0 |
0 |
| T15 |
0 |
2166 |
0 |
0 |
| T18 |
2023 |
315 |
0 |
0 |
| T19 |
584 |
0 |
0 |
0 |
| T22 |
0 |
1380 |
0 |
0 |
| T28 |
719 |
0 |
0 |
0 |
| T29 |
1623 |
0 |
0 |
0 |
| T30 |
1816 |
0 |
0 |
0 |
| T31 |
1563 |
0 |
0 |
0 |
| T32 |
0 |
217 |
0 |
0 |
| T40 |
3356 |
0 |
0 |
0 |
| T53 |
0 |
870 |
0 |
0 |
| T59 |
0 |
357 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10609786 |
10420700 |
0 |
0 |
| T1 |
1410 |
1352 |
0 |
0 |
| T2 |
1470 |
1416 |
0 |
0 |
| T3 |
2462 |
2391 |
0 |
0 |
| T4 |
1132 |
1003 |
0 |
0 |
| T5 |
2395 |
2239 |
0 |
0 |
| T10 |
3107 |
3040 |
0 |
0 |
| T18 |
2023 |
1953 |
0 |
0 |
| T28 |
719 |
619 |
0 |
0 |
| T29 |
1623 |
1536 |
0 |
0 |
| T30 |
1816 |
1724 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10609786 |
10420700 |
0 |
0 |
| T1 |
1410 |
1352 |
0 |
0 |
| T2 |
1470 |
1416 |
0 |
0 |
| T3 |
2462 |
2391 |
0 |
0 |
| T4 |
1132 |
1003 |
0 |
0 |
| T5 |
2395 |
2239 |
0 |
0 |
| T10 |
3107 |
3040 |
0 |
0 |
| T18 |
2023 |
1953 |
0 |
0 |
| T28 |
719 |
619 |
0 |
0 |
| T29 |
1623 |
1536 |
0 |
0 |
| T30 |
1816 |
1724 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10609786 |
10420700 |
0 |
0 |
| T1 |
1410 |
1352 |
0 |
0 |
| T2 |
1470 |
1416 |
0 |
0 |
| T3 |
2462 |
2391 |
0 |
0 |
| T4 |
1132 |
1003 |
0 |
0 |
| T5 |
2395 |
2239 |
0 |
0 |
| T10 |
3107 |
3040 |
0 |
0 |
| T18 |
2023 |
1953 |
0 |
0 |
| T28 |
719 |
619 |
0 |
0 |
| T29 |
1623 |
1536 |
0 |
0 |
| T30 |
1816 |
1724 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
10417909 |
1047324 |
0 |
0 |
| T5 |
2395 |
1738 |
0 |
0 |
| T6 |
15376 |
0 |
0 |
0 |
| T7 |
0 |
775 |
0 |
0 |
| T8 |
0 |
806 |
0 |
0 |
| T10 |
3107 |
2008 |
0 |
0 |
| T11 |
0 |
287 |
0 |
0 |
| T15 |
0 |
2166 |
0 |
0 |
| T16 |
0 |
152 |
0 |
0 |
| T18 |
2023 |
315 |
0 |
0 |
| T19 |
2322 |
24 |
0 |
0 |
| T28 |
719 |
0 |
0 |
0 |
| T29 |
1623 |
0 |
0 |
0 |
| T30 |
1816 |
0 |
0 |
0 |
| T31 |
1563 |
0 |
0 |
0 |
| T32 |
0 |
217 |
0 |
0 |
| T40 |
3356 |
0 |
0 |
0 |