Module Definition
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Module Instance : tb.dut.u_reg.u_intr_test_edn_cmd_req_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_intr_test_edn_fatal_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_alert_test_recov_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_alert_test_fatal_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_sw_cmd_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_reseed_cmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_generate_cmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T1 T2 T29  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_intr_test_edn_cmd_req_done
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T6 T60 T61  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_intr_test_edn_fatal_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T6 T60 T61  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_alert_test_recov_alert
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T29 T67 T69  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_alert_test_fatal_alert
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T29 T67 T69  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T1 T2 T3  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_reseed_cmd
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T18 T10 T5  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg.u_generate_cmd
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T18 T10 T5  30 unreachable assign qre = re;