Unified Coverage Report :: Module :: prim_packer_fifo

Module : prim_packer_fifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/edn-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	95.24			85.71	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	100.00	95.24			85.71	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.81	100.00	95.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.24	100.00

tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORE	LINE
98.81	100.00

tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :

SCORE	COND
95.24	95.24

tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T15,T32
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

SCORE	COND
98.81	95.24

tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T11,T44
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	84878288	9355131	0	7520
ValidOPairedWithReadyI_A	84878288	9355131	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84878288	9355131	0	7520
T1	1410	1114	0	1
T2	1470	1120	0	1
T3	17234	1280	0	7
T4	7924	515	0	7
T5	19160	0	0	8
T6	107632	3128	0	7
T10	24856	0	0	8
T11	0	1674	0	0
T18	16184	1000	0	8
T19	2322	1056	0	1
T22	0	494	0	0
T24	0	716	0	0
T28	5752	0	0	8
T29	12984	0	0	8
T30	14528	1377	0	8
T31	10941	1183	0	7
T40	3356	5075	0	1
T41	0	1465	0	0
T42	0	1023	0	0
T43	0	3984	0	0
T46	0	124	0	0
T53	0	525	0	0
T60	0	1383	0	0
T65	0	1153	0	0
T72	0	1678	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84878288	9355131	0	0
T1	1410	1114	0	0
T2	1470	1120	0	0
T3	17234	1280	0	0
T4	7924	515	0	0
T5	19160	0	0	0
T6	107632	3128	0	0
T10	24856	0	0	0
T11	0	1674	0	0
T18	16184	1000	0	0
T19	2322	1056	0	0
T22	0	494	0	0
T24	0	716	0	0
T28	5752	0	0	0
T29	12984	0	0	0
T30	14528	1377	0	0
T31	10941	1183	0	0
T40	3356	5075	0	0
T41	0	1465	0	0
T42	0	1023	0	0
T43	0	3984	0	0
T46	0	124	0	0
T53	0	525	0	0
T60	0	1383	0	0
T65	0	1153	0	0
T72	0	1678	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T15,T32
1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Line No.	Total	Covered	Percent
Branches		14	12	85.71
TERNARY	142	4	3	75.00
TERNARY	147	3	2	66.67
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	215564	0	940
ValidOPairedWithReadyI_A	10609786	215564	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	215564	0	940
T3	2462	9	0	1
T4	1132	41	0	1
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	683	0	1
T11	0	27	0	0
T15	0	448	0	0
T18	2023	199	0	1
T19	0	88	0	0
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T32	0	2	0	0
T33	0	41	0	0
T41	0	2	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	215564	0	0
T3	2462	9	0	0
T4	1132	41	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	683	0	0
T11	0	27	0	0
T15	0	448	0	0
T18	2023	199	0	0
T19	0	88	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T32	0	2	0	0
T33	0	41	0	0
T41	0	2	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T30

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T30
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T30

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T30

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T129,T227,T173
1	1	Covered	T1,T2,T4

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	7147449	0	940
ValidOPairedWithReadyI_A	10609786	7147449	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	7147449	0	940
T1	1410	1114	0	1
T2	1470	1120	0	1
T3	2462	0	0	1
T4	1132	515	0	1
T5	2395	0	0	1
T6	0	3128	0	0
T10	3107	0	0	1
T11	0	1563	0	0
T18	2023	0	0	1
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	1377	0	1
T31	0	1183	0	0
T40	0	2497	0	0
T60	0	1383	0	0
T65	0	1153	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	7147449	0	0
T1	1410	1114	0	0
T2	1470	1120	0	0
T3	2462	0	0	0
T4	1132	515	0	0
T5	2395	0	0	0
T6	0	3128	0	0
T10	3107	0	0	0
T11	0	1563	0	0
T18	2023	0	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	1377	0	0
T31	0	1183	0	0
T40	0	2497	0	0
T60	0	1383	0	0
T65	0	1153	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T11,T41

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T11,T41
1	0	Covered	T18,T11,T41
1	1	Covered	T18,T11,T41

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T11,T41

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T11,T41

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T11,T41
1	1	Covered	T18,T11,T41

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T11,T41

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T11,T41

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T11,T41

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T11,T41

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T11,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T11,T46
1	1	Covered	T18,T11,T41

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T18,T11,T41
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T18,T11,T41
0	0	1	Covered	T18,T11,T41
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T11,T41
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T18,T11,T41
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	344099	0	940
ValidOPairedWithReadyI_A	10609786	344099	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	344099	0	940
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	0	0	1
T11	0	111	0	0
T18	2023	126	0	1
T19	2322	0	0	1
T22	0	494	0	0
T24	0	716	0	0
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T40	3356	0	0	1
T41	0	1465	0	0
T42	0	1023	0	0
T43	0	1939	0	0
T46	0	124	0	0
T53	0	525	0	0
T72	0	1678	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	344099	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T11	0	111	0	0
T18	2023	126	0	0
T19	2322	0	0	0
T22	0	494	0	0
T24	0	716	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T40	3356	0	0	0
T41	0	1465	0	0
T42	0	1023	0	0
T43	0	1939	0	0
T46	0	124	0	0
T53	0	525	0	0
T72	0	1678	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T40

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T40
1	0	Covered	T3,T18,T40
1	1	Covered	T3,T18,T40

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T18,T40

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T18,T40

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T18,T40
1	1	Covered	T3,T18,T40

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T18,T40

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T18,T40

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T18,T40

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T18,T40

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T44,T228,T200
1	1	Covered	T3,T18,T40

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T3,T18,T40
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T18,T40
0	0	1	Covered	T3,T18,T40
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T18,T40
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T18,T40
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	452360	0	940
ValidOPairedWithReadyI_A	10609786	452360	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	452360	0	940
T3	2462	1280	0	1
T4	1132	0	0	1
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	0	0	1
T15	0	751	0	0
T18	2023	874	0	1
T19	0	1056	0	0
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T32	0	1006	0	0
T40	0	2578	0	0
T43	0	2045	0	0
T44	0	123	0	0
T45	0	1053	0	0
T59	0	1723	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	452360	0	0
T3	2462	1280	0	0
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T15	0	751	0	0
T18	2023	874	0	0
T19	0	1056	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T32	0	1006	0	0
T40	0	2578	0	0
T43	0	2045	0	0
T44	0	123	0	0
T45	0	1053	0	0
T59	0	1723	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T45

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T45
1	0	Covered	T3,T10,T45
1	1	Covered	T3,T10,T45

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T45

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T45

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T10,T45
1	1	Covered	T3,T10,T45

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T45

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T45

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T45

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T45

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T83,T229,T218
1	1	Covered	T3,T10,T45

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T3,T10,T45
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T10,T45
0	0	1	Covered	T3,T10,T45
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T10,T45
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T10,T45
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	433547	0	940
ValidOPairedWithReadyI_A	10609786	433547	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	433547	0	940
T3	2462	1575	0	1
T4	1132	0	0	1
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	1154	0	1
T18	2023	0	0	1
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T45	0	1062	0	0
T46	0	1259	0	0
T47	0	283	0	0
T54	0	1694	0	0
T80	0	1484	0	0
T81	0	860	0	0
T82	0	1166	0	0
T83	0	124	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	433547	0	0
T3	2462	1575	0	0
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	1154	0	0
T18	2023	0	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T45	0	1062	0	0
T46	0	1259	0	0
T47	0	283	0	0
T54	0	1694	0	0
T80	0	1484	0	0
T81	0	860	0	0
T82	0	1166	0	0
T83	0	124	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T28,T40

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T28,T40
1	0	Covered	T3,T28,T40
1	1	Covered	T3,T28,T40

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T28,T40

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T28,T40

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T28,T40
1	1	Covered	T3,T28,T40

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T28,T40

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T28,T40

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T28,T40

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T28,T40

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T28,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T230,T75
1	1	Covered	T3,T28,T40

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T3,T28,T40
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T28,T40
0	0	1	Covered	T3,T28,T40
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T28,T40
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T28,T40
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	204770	0	940
ValidOPairedWithReadyI_A	10609786	204770	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	204770	0	940
T3	2462	1199	0	1
T4	1132	0	0	1
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	0	0	1
T15	0	821	0	0
T18	2023	0	0	1
T27	0	1331	0	0
T28	719	438	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T40	0	2778	0	0
T50	0	1686	0	0
T68	0	723	0	0
T86	0	661	0	0
T87	0	679	0	0
T88	0	1083	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	204770	0	0
T3	2462	1199	0	0
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T15	0	821	0	0
T18	2023	0	0	0
T27	0	1331	0	0
T28	719	438	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T40	0	2778	0	0
T50	0	1686	0	0
T68	0	723	0	0
T86	0	661	0	0
T87	0	679	0	0
T88	0	1083	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T40,T42

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T40,T42
1	0	Covered	T3,T40,T53
1	1	Covered	T3,T40,T42

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T40,T42

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T40,T53

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T40,T53
1	1	Covered	T3,T40,T53

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T40,T53

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T40,T53

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T40,T53

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T40,T53

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T40,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T91,T92
1	1	Covered	T3,T40,T53

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T3,T40,T53
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T40,T53
0	0	1	Covered	T3,T40,T53
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T40,T53
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T40,T53
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	417695	0	940
ValidOPairedWithReadyI_A	10609786	417695	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	417695	0	940
T3	2462	1544	0	1
T4	1132	0	0	1
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	0	0	1
T18	2023	0	0	1
T23	0	920	0	0
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T40	0	2776	0	0
T42	0	1781	0	0
T52	0	739	0	0
T53	0	554	0	0
T54	0	1334	0	0
T90	0	1353	0	0
T91	0	1138	0	0
T92	0	60	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	417695	0	0
T3	2462	1544	0	0
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T18	2023	0	0	0
T23	0	920	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T40	0	2776	0	0
T42	0	1781	0	0
T52	0	739	0	0
T53	0	554	0	0
T54	0	1334	0	0
T90	0	1353	0	0
T91	0	1138	0	0
T92	0	60	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
TOTAL		24	24	100.00
ALWAYS	82	7	7	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	127	3	3	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00

81                        always_ff @(posedge clk_i or negedge rst_ni) begin
82         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
83         1/1                depth_q <= '0;
           Tests:       T1 T2 T3 
84         1/1                data_q  <= '0;
           Tests:       T1 T2 T3 
85         1/1                clr_q   <= 1'b1;
           Tests:       T1 T2 T3 
86                          end else begin
87         1/1                depth_q <= depth_d;
           Tests:       T1 T2 T3 
88         1/1                data_q  <= data_d;
           Tests:       T1 T2 T3 
89         1/1                clr_q   <= clr_d;
           Tests:       T1 T2 T3 
90                          end
91                        end
92                      
93                        // flop for handling reset case for clr
94         1/1            assign clr_d = clr_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign depth_o = depth_q;
           Tests:       T1 T2 T3 
97                      
98                        if (InW < OutW) begin : gen_pack_mode
99                          logic [MaxW-1:0] wdata_shifted;
100                     
101                         assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW);
102                         assign clear_status = (rready_i && rvalid_o) || clr_q;
103                         assign clear_data = (ClearOnRead && clear_status) || clr_q;
104                         assign load_data = wvalid_i && wready_o;
105                     
106                         assign depth_d =  clear_status ? '0 :
107                                load_data ? (depth_q + DepthOne):
108                                depth_q;
109                     
110                         assign data_d = clear_data ? '0 :
111                                load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) :
112                                data_q;
113                     
114                         // set outputs
115                         assign wready_o = !(depth_q == FullDepth) && !clr_q;
116                         assign rdata_o =  data_q;
117                         assign rvalid_o = (depth_q == FullDepth) && !clr_q;
118                     
119                       end else begin : gen_unpack_mode
120                         logic [MaxW-1:0] rdata_shifted;
121                         logic            pull_data;
122                         logic [DepthW:0] ptr_q, ptr_d;
123                         logic [DepthW:0] lsb_is_one;
124                         logic [DepthW:0] max_value;
125                     
126                         always_ff @(posedge clk_i or negedge rst_ni) begin
127        1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
128        1/1                  ptr_q   <= '0;
           Tests:       T1 T2 T3 
129                           end else begin
130        1/1                  ptr_q   <= ptr_d;
           Tests:       T1 T2 T3 
131                           end
132                         end
133                     
134                         assign lsb_is_one = {{DepthW{1'b0}},1'b1};
135                         assign max_value = FullDepth;
136        1/1              assign rdata_shifted = data_q >> ptr_q*OutW;
           Tests:       T1 T2 T3 
137        1/1              assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
           Tests:       T1 T2 T3 
138        1/1              assign clear_data = (ClearOnRead && clear_status) || clr_q;
           Tests:       T1 T2 T3 
139        1/1              assign load_data = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
140        1/1              assign pull_data = rvalid_o && rready_i;
           Tests:       T1 T2 T3 
141                     
142        1/1              assign depth_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
143                                load_data ? max_value :
144                                pull_data ? (depth_q - DepthOne) :
145                                depth_q;
146                     
147        1/1              assign ptr_d =  clear_status ? '0 :
           Tests:       T1 T2 T3 
148                                pull_data ? (ptr_q + DepthOne) :
149                                ptr_q;
150                     
151        1/1              assign data_d = clear_data ? '0 :
           Tests:       T1 T2 T3 
152                                load_data ? wdata_i :
153                                data_q;
154                     
155                         // set outputs
156        1/1              assign wready_o = (depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
157        1/1              assign rdata_o =  rdata_shifted[OutW-1:0];
           Tests:       T1 T2 T3 
158        1/1              assign rvalid_o = !(depth_q == '0) && !clr_q;
           Tests:       T1 T2 T3 
159                     
160                         // Avoid possible lint errors in case InW > OutW.
161                         if (InW > OutW) begin : gen_unused
162                           logic [MaxW-MinW-1:0] unused_rdata_shifted;
163        1/1                assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW];
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       137
 EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
             --------------------------1--------------------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T56,T57

 LINE       137
 SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
                 ----1---    -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T56,T57
1	0	Covered	T3,T56,T57
1	1	Covered	T3,T56,T57

 LINE       137
 SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T56,T57

 LINE       138
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       139
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T56,T57

 LINE       140
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T56,T57
1	1	Covered	T3,T56,T57

 LINE       142
 EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T56,T57

 LINE       142
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T56,T57

 LINE       147
 EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T56,T57

 LINE       151
 EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       151
 SUB-EXPRESSION (load_data ? wdata_i : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T56,T57

 LINE       156
 EXPRESSION ((depth_q == '0) && ((!clr_q)))
             -------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T56,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       156
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
             ----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T95,T96,T97
1	1	Covered	T3,T56,T57

 LINE       158
 SUB-EXPRESSION ( ! (depth_q == '0) )
                    -------1-------

-1-	Status	Tests
0	Covered	T3,T56,T57
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (depth_q == '0)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Line No.	Total	Covered	Percent
Branches		14	14	100.00
TERNARY	142	4	4	100.00
TERNARY	147	3	3	100.00
TERNARY	151	3	3	100.00
IF	82	2	2	100.00
IF	127	2	2	100.00

142            assign depth_d =  clear_status ? '0 :
                                              -1-  
                                              ==>  
143                   load_data ? max_value :
                                -2-  
                                ==>  
144                   pull_data ? (depth_q - DepthOne) :
                                -3-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T56,T57
0	0	1	Covered	T3,T56,T57
0	0	0	Covered	T1,T2,T3

147            assign ptr_d =  clear_status ? '0 :
                                            -1-  
                                            ==>  
148                   pull_data ? (ptr_q + DepthOne) :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T56,T57
0	0	Covered	T1,T2,T3

151            assign data_d = clear_data ? '0 :
                                          -1-  
                                          ==>  
152                   load_data ? wdata_i :
                                -2-  
                                ==>  
                                ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T56,T57
0	0	Covered	T1,T2,T3

82             if (!rst_ni) begin
               -1-  
83               depth_q <= '0;
                 ==>
84               data_q  <= '0;
85               clr_q   <= 1'b1;
86             end else begin
87               depth_q <= depth_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

127              if (!rst_ni) begin
                 -1-  
128                ptr_q   <= '0;
                   ==>
129              end else begin
130                ptr_q   <= ptr_d;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	10609786	139647	0	940
ValidOPairedWithReadyI_A	10609786	139647	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	139647	0	940
T3	2462	1517	0	1
T4	1132	0	0	1
T5	2395	0	0	1
T6	15376	0	0	1
T10	3107	0	0	1
T18	2023	0	0	1
T25	0	1140	0	0
T28	719	0	0	1
T29	1623	0	0	1
T30	1816	0	0	1
T31	1563	0	0	1
T34	0	225	0	0
T54	0	1395	0	0
T56	0	767	0	0
T57	0	1810	0	0
T94	0	779	0	0
T95	0	87	0	0
T96	0	88	0	0
T97	0	111	0	0

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609786	139647	0	0
T3	2462	1517	0	0
T4	1132	0	0	0
T5	2395	0	0	0
T6	15376	0	0	0
T10	3107	0	0	0
T18	2023	0	0	0
T25	0	1140	0	0
T28	719	0	0	0
T29	1623	0	0	0
T30	1816	0	0	0
T31	1563	0	0	0
T34	0	225	0	0
T54	0	1395	0	0
T56	0	767	0	0
T57	0	1810	0	0
T94	0	779	0	0
T95	0	87	0	0
T96	0	88	0	0
T97	0	111	0	0