Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	119	1			T19	1		T21	1		T37	1
auto_req_mode	139	1			T9	1		T10	1		T14	1
sw_mode	2308	1			T1	1		T2	1		T5	3

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

298

1

T19

1

T21

1

T36

1

single

102

1

T9

1

T37

1

T10

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1158	1			T1	1		T19	1		T21	1
auto[2]	84	1			T69	1		T235	23		T305	1
auto[3]	47	1			T119	1		T306	2		T247	30
auto[4]	176	1			T2	1		T39	9		T14	1
auto[5]	16	1			T120	11		T241	1		T307	1
auto[6]	121	1			T42	1		T34	29		T250	3
auto[7]	964	1			T36	1		T25	1		T52	12

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[3]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	84	1			T19	1		T21	1		T37	1
auto[1]	auto_req_mode	80	1			T9	1		T10	1		T18	1
auto[1]	sw_mode	994	1			T1	1		T5	3		T23	1
auto[2]	boot_req_mode	5	1			T69	1		T308	1		T309	1
auto[2]	auto_req_mode	5	1			T310	1		T311	1		T13	1
auto[2]	sw_mode	74	1			T235	23		T305	1		T312	44
auto[3]	auto_req_mode	4	1			T313	1		T314	1		T315	1
auto[3]	sw_mode	43	1			T119	1		T306	2		T247	30
auto[4]	boot_req_mode	1	1			T316	1		-	-		-	-
auto[4]	auto_req_mode	3	1			T14	1		T317	1		T318	1
auto[4]	sw_mode	172	1			T2	1		T39	9		T319	9
auto[5]	boot_req_mode	1	1			T320	1		-	-		-	-
auto[5]	auto_req_mode	1	1			T321	1		-	-		-	-
auto[5]	sw_mode	14	1			T120	11		T241	1		T307	1
auto[6]	boot_req_mode	1	1			T322	1		-	-		-	-
auto[6]	auto_req_mode	9	1			T42	1		T323	1		T324	1
auto[6]	sw_mode	111	1			T34	29		T250	3		T243	51
auto[7]	boot_req_mode	27	1			T48	1		T104	1		T325	1
auto[7]	auto_req_mode	37	1			T11	1		T103	1		T12	1
auto[7]	sw_mode	900	1			T36	1		T25	1		T52	12