Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

334680

1

T1

6

T2

10

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	204986	1			T1	20		T2	59		T3	16
values[0x0]	134099	1			T1	3		T2	7		T3	8
values[0x1]	149799	1			T1	4		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	103498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

385386

1

T1

7

T2

30

T3

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1947	1			T2	2		T20	2		T28	1
valid_sources[0x01]	1671	1			T36	3		T39	4		T14	3
valid_sources[0x02]	1451	1			T20	1		T5	2		T26	2
valid_sources[0x03]	1893	1			T2	1		T39	3		T10	5
valid_sources[0x04]	1827	1			T28	2		T36	1		T10	1
valid_sources[0x05]	1996	1			T2	1		T5	1		T39	4
valid_sources[0x06]	2573	1			T9	8		T26	1		T39	2
valid_sources[0x07]	2015	1			T1	6		T36	1		T39	6
valid_sources[0x08]	1664	1			T5	1		T62	1		T14	3
valid_sources[0x09]	1938	1			T9	3		T26	1		T39	1
valid_sources[0x0a]	1709	1			T39	1		T61	1		T25	1
valid_sources[0x0b]	1712	1			T5	1		T28	1		T39	2
valid_sources[0x0c]	2139	1			T20	1		T5	2		T36	1
valid_sources[0x0d]	2231	1			T2	1		T21	169		T36	2
valid_sources[0x0e]	2395	1			T20	1		T5	1		T36	2
valid_sources[0x0f]	1666	1			T39	1		T61	1		T10	1
valid_sources[0x10]	2510	1			T36	1		T39	3		T10	2
valid_sources[0x11]	1795	1			T5	1		T36	1		T14	1
valid_sources[0x12]	1616	1			T39	1		T61	1		T10	2
valid_sources[0x13]	1994	1			T39	1		T14	1		T7	1
valid_sources[0x14]	1925	1			T9	7		T36	1		T39	4
valid_sources[0x15]	1537	1			T9	1		T39	2		T7	1
valid_sources[0x16]	1700	1			T20	2		T5	3		T36	1
valid_sources[0x17]	1908	1			T20	1		T36	2		T39	2
valid_sources[0x18]	2114	1			T36	2		T37	4		T26	1
valid_sources[0x19]	1534	1			T5	5		T36	1		T39	1
valid_sources[0x1a]	1811	1			T1	2		T20	1		T5	3
valid_sources[0x1b]	1811	1			T5	1		T36	1		T39	1
valid_sources[0x1c]	1832	1			T39	3		T10	1		T14	4
valid_sources[0x1d]	1479	1			T36	5		T39	2		T61	1
valid_sources[0x1e]	1984	1			T36	3		T10	2		T14	2
valid_sources[0x1f]	1714	1			T5	1		T26	1		T39	4
valid_sources[0x20]	2107	1			T2	1		T22	2		T28	1
valid_sources[0x21]	1744	1			T3	28		T25	1		T16	4
valid_sources[0x22]	2439	1			T36	1		T26	1		T39	4
valid_sources[0x23]	2164	1			T36	1		T10	2		T17	2
valid_sources[0x24]	2028	1			T28	1		T39	4		T7	2
valid_sources[0x25]	1677	1			T5	2		T26	3		T39	2
valid_sources[0x26]	1704	1			T5	1		T26	1		T39	3
valid_sources[0x27]	1705	1			T39	1		T16	7		T17	3
valid_sources[0x28]	2007	1			T2	2		T5	1		T26	1
valid_sources[0x29]	2368	1			T5	1		T62	1		T16	2
valid_sources[0x2a]	2175	1			T39	2		T62	1		T16	3
valid_sources[0x2b]	1832	1			T1	1		T5	2		T39	2
valid_sources[0x2c]	2390	1			T2	1		T39	2		T62	1
valid_sources[0x2d]	1688	1			T22	2		T28	1		T39	4
valid_sources[0x2e]	1973	1			T5	3		T36	1		T39	2
valid_sources[0x2f]	1713	1			T20	1		T36	1		T39	1
valid_sources[0x30]	1690	1			T39	9		T10	1		T25	1
valid_sources[0x31]	1583	1			T5	9		T28	1		T36	1
valid_sources[0x32]	2509	1			T1	2		T24	34		T36	3
valid_sources[0x33]	2357	1			T26	1		T39	4		T10	1
valid_sources[0x34]	1866	1			T20	1		T10	2		T14	3
valid_sources[0x35]	1984	1			T20	1		T36	2		T14	1
valid_sources[0x36]	1774	1			T2	1		T62	1		T25	1
valid_sources[0x37]	1549	1			T36	2		T39	1		T16	7
valid_sources[0x38]	2888	1			T20	1		T5	3		T36	1
valid_sources[0x39]	1754	1			T2	1		T20	1		T9	4
valid_sources[0x3a]	1665	1			T5	9		T36	1		T39	2
valid_sources[0x3b]	1814	1			T39	4		T16	3		T251	3
valid_sources[0x3c]	2017	1			T39	6		T16	5		T128	23
valid_sources[0x3d]	1833	1			T39	2		T14	1		T16	3
valid_sources[0x3e]	1867	1			T39	1		T10	2		T25	1
valid_sources[0x3f]	2525	1			T36	1		T39	2		T16	4
valid_sources[0x40]	1599	1			T36	3		T39	1		T14	2
valid_sources[0x41]	1485	1			T1	4		T5	1		T16	2
valid_sources[0x42]	1684	1			T2	2		T9	3		T39	2
valid_sources[0x43]	1733	1			T2	1		T20	1		T36	1
valid_sources[0x44]	1842	1			T20	1		T5	1		T36	3
valid_sources[0x45]	1793	1			T5	5		T36	1		T39	3
valid_sources[0x46]	1650	1			T1	1		T5	7		T62	1
valid_sources[0x47]	1775	1			T2	1		T20	1		T5	3
valid_sources[0x48]	2063	1			T16	6		T17	1		T124	1
valid_sources[0x49]	1698	1			T2	1		T36	2		T39	1
valid_sources[0x4a]	2152	1			T36	3		T39	1		T27	1
valid_sources[0x4b]	1813	1			T61	1		T14	3		T16	6
valid_sources[0x4c]	1489	1			T36	1		T39	2		T25	1
valid_sources[0x4d]	1666	1			T28	1		T36	2		T26	2
valid_sources[0x4e]	1855	1			T2	1		T5	4		T39	1
valid_sources[0x4f]	1942	1			T20	1		T5	1		T39	1
valid_sources[0x50]	1559	1			T2	1		T39	2		T16	5
valid_sources[0x51]	2006	1			T5	1		T36	2		T39	2
valid_sources[0x52]	2198	1			T2	1		T28	1		T36	1
valid_sources[0x53]	1729	1			T5	1		T36	2		T39	5
valid_sources[0x54]	1578	1			T28	1		T36	2		T39	3
valid_sources[0x55]	2402	1			T9	1		T16	2		T17	1
valid_sources[0x56]	1762	1			T36	1		T39	5		T14	1
valid_sources[0x57]	1805	1			T36	1		T26	2		T39	2
valid_sources[0x58]	2343	1			T20	2		T28	1		T36	1
valid_sources[0x59]	1791	1			T36	2		T39	1		T61	1
valid_sources[0x5a]	1774	1			T39	3		T27	1		T16	4
valid_sources[0x5b]	1868	1			T2	2		T5	1		T39	5
valid_sources[0x5c]	1766	1			T5	3		T36	1		T39	1
valid_sources[0x5d]	1746	1			T2	1		T5	3		T9	1
valid_sources[0x5e]	1863	1			T39	2		T10	1		T14	1
valid_sources[0x5f]	1632	1			T19	5		T5	7		T28	1
valid_sources[0x60]	1453	1			T5	1		T26	1		T39	2
valid_sources[0x61]	1968	1			T5	3		T36	1		T26	1
valid_sources[0x62]	2195	1			T1	2		T2	3		T5	2
valid_sources[0x63]	2003	1			T22	2		T36	1		T26	2
valid_sources[0x64]	1672	1			T39	4		T10	2		T7	2
valid_sources[0x65]	1750	1			T5	2		T36	1		T26	1
valid_sources[0x66]	1981	1			T20	1		T5	1		T36	1
valid_sources[0x67]	2035	1			T28	1		T36	2		T39	3
valid_sources[0x68]	2310	1			T36	1		T39	4		T10	2
valid_sources[0x69]	1690	1			T5	4		T36	3		T26	1
valid_sources[0x6a]	2143	1			T39	2		T14	1		T16	4
valid_sources[0x6b]	1679	1			T20	1		T39	3		T14	1
valid_sources[0x6c]	2281	1			T5	1		T36	2		T39	2
valid_sources[0x6d]	1664	1			T5	1		T39	3		T14	1
valid_sources[0x6e]	1987	1			T36	1		T39	1		T14	1
valid_sources[0x6f]	2036	1			T20	2		T5	3		T36	1
valid_sources[0x70]	2183	1			T28	1		T39	3		T25	2
valid_sources[0x71]	1920	1			T39	1		T10	1		T16	6
valid_sources[0x72]	1731	1			T28	2		T36	2		T26	3
valid_sources[0x73]	2186	1			T20	1		T36	2		T62	1
valid_sources[0x74]	2198	1			T2	2		T5	3		T36	2
valid_sources[0x75]	1959	1			T5	1		T39	1		T14	1
valid_sources[0x76]	3387	1			T20	1		T5	3		T36	1
valid_sources[0x77]	1817	1			T20	1		T5	1		T36	2
valid_sources[0x78]	2306	1			T25	1		T14	1		T16	5
valid_sources[0x79]	1897	1			T5	2		T36	2		T39	3
valid_sources[0x7a]	2164	1			T5	2		T28	1		T36	1
valid_sources[0x7b]	2106	1			T2	2		T9	2		T36	1
valid_sources[0x7c]	1806	1			T20	1		T39	1		T62	2
valid_sources[0x7d]	1625	1			T5	2		T39	2		T62	1
valid_sources[0x7e]	2087	1			T9	8		T39	2		T16	4
valid_sources[0x7f]	2062	1			T5	1		T28	1		T39	5
valid_sources[0x80]	2523	1			T5	2		T39	2		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

90419

1

T1

2

T2

3

T3

3

values[0x0]

all_enables

biggest_size

123109

1

T1

2

T2

6

T3

5

values[0x1]

all_enables

biggest_size

121152

1

T1

2

T2

1

T3

1