Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1854	1			T21	1		T5	1		T9	9
non_zero_bins[1]	1332	1			T21	1		T5	3		T9	1
zero	6237	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	342	1			T5	1		T39	1		T52	3
uni	2210	1			T1	1		T2	1		T21	2
gen	3217	1			T1	1		T2	1		T3	1
res	683	1			T21	1		T9	4		T36	1
ins	2971	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6040

1

T1

3

T2

2

T3

2

mubi_true

3383

1

T2

1

T19

4

T20

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

34

1

T139

1

T91

1

T184

1

pass

9389

1

T1

3

T2

3

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	78	1			T116	3		T293	1		T120	1
upd	non_zero_bins[0]	pass	mubi_true	81	1			T52	1		T128	1		T33	1
upd	non_zero_bins[1]	pass	mubi_false	58	1			T116	1		T239	1		T117	1
upd	non_zero_bins[1]	pass	mubi_true	61	1			T39	1		T52	1		T120	1
upd	zero	pass	mubi_false	31	1			T5	1		T52	1		T122	1
upd	zero	pass	mubi_true	33	1			T34	1		T35	2		T212	1
uni	zero	pass	mubi_false	1652	1			T1	1		T21	2		T5	2
uni	zero	pass	mubi_true	558	1			T2	1		T5	2		T23	1
gen	non_zero_bins[0]	pass	mubi_false	347	1			T39	2		T14	1		T52	1
gen	non_zero_bins[0]	pass	mubi_true	363	1			T9	4		T36	1		T39	2
gen	non_zero_bins[1]	pass	mubi_false	254	1			T21	1		T52	2		T18	3
gen	non_zero_bins[1]	pass	mubi_true	258	1			T5	1		T10	3		T14	3
gen	zero	fail	mubi_false	30	1			T139	1		T91	1		T184	1
gen	zero	pass	mubi_false	1304	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	661	1			T19	2		T20	3		T37	1
res	non_zero_bins[0]	pass	mubi_false	165	1			T21	1		T9	3		T52	1
res	non_zero_bins[0]	pass	mubi_true	151	1			T39	1		T85	3		T94	4
res	non_zero_bins[1]	pass	mubi_false	120	1			T36	1		T14	2		T42	2
res	non_zero_bins[1]	pass	mubi_true	102	1			T9	1		T18	4		T108	2
res	zero	fail	mubi_false	4	1			T176	1		T177	1		T178	1
res	zero	pass	mubi_false	98	1			T10	4		T45	3		T79	3
res	zero	pass	mubi_true	43	1			T33	1		T69	1		T99	2
ins	non_zero_bins[0]	pass	mubi_false	346	1			T5	1		T9	2		T39	2
ins	non_zero_bins[0]	pass	mubi_true	323	1			T39	2		T52	4		T64	1
ins	non_zero_bins[1]	pass	mubi_false	232	1			T5	1		T39	1		T52	4
ins	non_zero_bins[1]	pass	mubi_true	247	1			T5	1		T10	2		T14	1
ins	zero	pass	mubi_false	1321	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	502	1			T19	2		T20	1		T26	3

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded