Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.64 100.00 78.57 100.00 100.00 u_prim_fifo_sync_rescmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_secure_ptrs.u_rptr 100.00 100.00
gen_secure_ptrs.u_wptr 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.64 100.00 78.57 100.00 100.00 u_prim_fifo_sync_gencmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_secure_ptrs.u_rptr 100.00 100.00
gen_secure_ptrs.u_wptr 100.00 100.00

Line Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00

40 // Derive real read and write pointers by truncating the internal 'wrap' pointers. 41 1/1 assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0]; Tests: T1 T2 T3  42 1/1 assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0]; Tests: T1 T2 T3  43 44 // Extract the MSB of the 'wrap' pointers. 45 logic wptr_wrap_msb, rptr_wrap_msb; 46 1/1 assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1]; Tests: T1 T2 T3  47 1/1 assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1]; Tests: T1 T2 T3  48 49 // Wrap pointers when they have reached the maximum value and are about to get incremented. 50 logic wptr_wrap_set, rptr_wrap_set; 51 1/1 assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1)); Tests: T1 T2 T3  52 1/1 assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1)); Tests: T1 T2 T3  53 54 // When wrapping, invert the MSB and reset all lower bits to zero. 55 1/1 assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}}; Tests: T1 T2 T3  56 1/1 assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}}; Tests: T1 T2 T3  57 58 // Full when both 'wrap' counters have a different MSB but all lower bits are equal. 59 1/1 assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}}); Tests: T1 T2 T3  60 // Empty when both 'wrap' counters are equal in all bits including the MSB. 61 1/1 assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q; Tests: T1 T2 T3  62 63 // The current depth is equal to: 64 // - when full: the maximum depth; 65 // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers; 66 // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference 67 // of the real pointers. 68 1/1 assign depth_o = full_o ? DepthW'(Depth) : Tests: T1 T2 T3  69 wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) : 70 DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o); 71 72 if (Secure) begin : gen_secure_ptrs 73 logic wptr_err; 74 prim_count #( 75 .Width(WrapPtrW) 76 ) u_wptr ( 77 .clk_i, 78 .rst_ni, 79 .clr_i, 80 .set_i(wptr_wrap_set), 81 .set_cnt_i(wptr_wrap_set_cnt), 82 .incr_en_i(incr_wptr_i), 83 .decr_en_i(1'b0), 84 .step_i(WrapPtrW'(1'b1)), 85 .commit_i(1'b1), 86 .cnt_o(wptr_wrap_cnt_q), 87 .cnt_after_commit_o(), 88 .err_o(wptr_err) 89 ); 90 91 logic rptr_err; 92 prim_count #( 93 .Width(WrapPtrW) 94 ) u_rptr ( 95 .clk_i, 96 .rst_ni, 97 .clr_i, 98 .set_i(rptr_wrap_set), 99 .set_cnt_i(rptr_wrap_set_cnt), 100 .incr_en_i(incr_rptr_i), 101 .decr_en_i(1'b0), 102 .step_i(WrapPtrW'(1'b1)), 103 .commit_i(1'b1), 104 .cnt_o(rptr_wrap_cnt_q), 105 .cnt_after_commit_o(), 106 .err_o(rptr_err) 107 ); 108 109 1/1 assign err_o = wptr_err | rptr_err; Tests: T1 T2 T3 

Cond Coverage for Module : prim_fifo_sync_cnt
TotalCoveredPercent
Conditions2323100.00
Logical2323100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T6,T10
10CoveredT4,T9,T6
11CoveredT9,T6,T10

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T14
10CoveredT9,T10,T14
11CoveredT9,T10,T14

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T14

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T14
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T14
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T17
10CoveredT15,T16,T17

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00


68 assign depth_o = full_o ? DepthW'(Depth) : -1- ==> 69 wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T9,T6,T10
0 1 Covered T1,T2,T3
0 0 Covered T9,T10,T14

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00

40 // Derive real read and write pointers by truncating the internal 'wrap' pointers. 41 1/1 assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0]; Tests: T1 T2 T3  42 1/1 assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0]; Tests: T1 T2 T3  43 44 // Extract the MSB of the 'wrap' pointers. 45 logic wptr_wrap_msb, rptr_wrap_msb; 46 1/1 assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1]; Tests: T1 T2 T3  47 1/1 assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1]; Tests: T1 T2 T3  48 49 // Wrap pointers when they have reached the maximum value and are about to get incremented. 50 logic wptr_wrap_set, rptr_wrap_set; 51 1/1 assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1)); Tests: T1 T2 T3  52 1/1 assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1)); Tests: T1 T2 T3  53 54 // When wrapping, invert the MSB and reset all lower bits to zero. 55 1/1 assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}}; Tests: T1 T2 T3  56 1/1 assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}}; Tests: T1 T2 T3  57 58 // Full when both 'wrap' counters have a different MSB but all lower bits are equal. 59 1/1 assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}}); Tests: T1 T2 T3  60 // Empty when both 'wrap' counters are equal in all bits including the MSB. 61 1/1 assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q; Tests: T1 T2 T3  62 63 // The current depth is equal to: 64 // - when full: the maximum depth; 65 // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers; 66 // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference 67 // of the real pointers. 68 1/1 assign depth_o = full_o ? DepthW'(Depth) : Tests: T1 T2 T3  69 wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) : 70 DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o); 71 72 if (Secure) begin : gen_secure_ptrs 73 logic wptr_err; 74 prim_count #( 75 .Width(WrapPtrW) 76 ) u_wptr ( 77 .clk_i, 78 .rst_ni, 79 .clr_i, 80 .set_i(wptr_wrap_set), 81 .set_cnt_i(wptr_wrap_set_cnt), 82 .incr_en_i(incr_wptr_i), 83 .decr_en_i(1'b0), 84 .step_i(WrapPtrW'(1'b1)), 85 .commit_i(1'b1), 86 .cnt_o(wptr_wrap_cnt_q), 87 .cnt_after_commit_o(), 88 .err_o(wptr_err) 89 ); 90 91 logic rptr_err; 92 prim_count #( 93 .Width(WrapPtrW) 94 ) u_rptr ( 95 .clk_i, 96 .rst_ni, 97 .clr_i, 98 .set_i(rptr_wrap_set), 99 .set_cnt_i(rptr_wrap_set_cnt), 100 .incr_en_i(incr_rptr_i), 101 .decr_en_i(1'b0), 102 .step_i(WrapPtrW'(1'b1)), 103 .commit_i(1'b1), 104 .cnt_o(rptr_wrap_cnt_q), 105 .cnt_after_commit_o(), 106 .err_o(rptr_err) 107 ); 108 109 1/1 assign err_o = wptr_err | rptr_err; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2323100.00
Logical2323100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T14,T27
10CoveredT4,T9,T6
11CoveredT9,T14,T18

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T14,T27

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT14,T18,T42
10CoveredT9,T10,T14
11CoveredT9,T14,T18

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T14,T18

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T14,T108

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T14,T108

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT9,T14,T18
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT9,T14,T18
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T17
10CoveredT15,T16,T17

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00


68 assign depth_o = full_o ? DepthW'(Depth) : -1- ==> 69 wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T9,T14,T108
0 1 Covered T1,T2,T3
0 0 Covered T9,T14,T18

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00

40 // Derive real read and write pointers by truncating the internal 'wrap' pointers. 41 1/1 assign wptr_o = wptr_wrap_cnt_q[PtrW-1:0]; Tests: T1 T2 T3  42 1/1 assign rptr_o = rptr_wrap_cnt_q[PtrW-1:0]; Tests: T1 T2 T3  43 44 // Extract the MSB of the 'wrap' pointers. 45 logic wptr_wrap_msb, rptr_wrap_msb; 46 1/1 assign wptr_wrap_msb = wptr_wrap_cnt_q[WrapPtrW-1]; Tests: T1 T2 T3  47 1/1 assign rptr_wrap_msb = rptr_wrap_cnt_q[WrapPtrW-1]; Tests: T1 T2 T3  48 49 // Wrap pointers when they have reached the maximum value and are about to get incremented. 50 logic wptr_wrap_set, rptr_wrap_set; 51 1/1 assign wptr_wrap_set = incr_wptr_i & (wptr_o == PtrW'(Depth-1)); Tests: T1 T2 T3  52 1/1 assign rptr_wrap_set = incr_rptr_i & (rptr_o == PtrW'(Depth-1)); Tests: T1 T2 T3  53 54 // When wrapping, invert the MSB and reset all lower bits to zero. 55 1/1 assign wptr_wrap_set_cnt = {~wptr_wrap_msb, {(WrapPtrW-1){1'b0}}}; Tests: T1 T2 T3  56 1/1 assign rptr_wrap_set_cnt = {~rptr_wrap_msb, {(WrapPtrW-1){1'b0}}}; Tests: T1 T2 T3  57 58 // Full when both 'wrap' counters have a different MSB but all lower bits are equal. 59 1/1 assign full_o = wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW-1){1'b0}}}); Tests: T1 T2 T3  60 // Empty when both 'wrap' counters are equal in all bits including the MSB. 61 1/1 assign empty_o = wptr_wrap_cnt_q == rptr_wrap_cnt_q; Tests: T1 T2 T3  62 63 // The current depth is equal to: 64 // - when full: the maximum depth; 65 // - when both or none of the 'wrap' pointers are wrapped: the difference of the real pointers; 66 // - when only one of the two 'wrap' pointers is wrapped: the maximum depth minus the difference 67 // of the real pointers. 68 1/1 assign depth_o = full_o ? DepthW'(Depth) : Tests: T1 T2 T3  69 wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) : 70 DepthW'(Depth) - DepthW'(rptr_o) + DepthW'(wptr_o); 71 72 if (Secure) begin : gen_secure_ptrs 73 logic wptr_err; 74 prim_count #( 75 .Width(WrapPtrW) 76 ) u_wptr ( 77 .clk_i, 78 .rst_ni, 79 .clr_i, 80 .set_i(wptr_wrap_set), 81 .set_cnt_i(wptr_wrap_set_cnt), 82 .incr_en_i(incr_wptr_i), 83 .decr_en_i(1'b0), 84 .step_i(WrapPtrW'(1'b1)), 85 .commit_i(1'b1), 86 .cnt_o(wptr_wrap_cnt_q), 87 .cnt_after_commit_o(), 88 .err_o(wptr_err) 89 ); 90 91 logic rptr_err; 92 prim_count #( 93 .Width(WrapPtrW) 94 ) u_rptr ( 95 .clk_i, 96 .rst_ni, 97 .clr_i, 98 .set_i(rptr_wrap_set), 99 .set_cnt_i(rptr_wrap_set_cnt), 100 .incr_en_i(incr_rptr_i), 101 .decr_en_i(1'b0), 102 .step_i(WrapPtrW'(1'b1)), 103 .commit_i(1'b1), 104 .cnt_o(rptr_wrap_cnt_q), 105 .cnt_after_commit_o(), 106 .err_o(rptr_err) 107 ); 108 109 1/1 assign err_o = wptr_err | rptr_err; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2323100.00
Logical2323100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T6,T10
10CoveredT4,T9,T6
11CoveredT9,T6,T10

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT9,T10,T14
10CoveredT9,T10,T14
11CoveredT10,T14,T18

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T14

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T6,T10

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T14
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT9,T10,T14
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T17
10CoveredT15,T16,T17

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00


68 assign depth_o = full_o ? DepthW'(Depth) : -1- ==> 69 wptr_wrap_msb == rptr_wrap_msb ? DepthW'(wptr_o) - DepthW'(rptr_o) : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T9,T6,T10
0 1 Covered T1,T2,T3
0 0 Covered T9,T10,T14

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%