Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	123	1			T25	1		T30	1		T31	1
auto_req_mode	143	1			T10	1		T14	1		T15	1
sw_mode	1892	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

288

1

T3

1

T10

1

T25

1

single

102

1

T15

1

T47

1

T322

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1030	1			T2	1		T10	1		T25	1
auto[2]	82	1			T1	1		T330	1		T81	1
auto[3]	76	1			T263	3		T331	1		T332	1
auto[4]	23	1			T333	11		T334	3		T335	1
auto[5]	20	1			T231	14		T336	1		T337	1
auto[6]	128	1			T86	1		T83	1		T338	13
auto[7]	799	1			T3	1		T26	1		T30	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[6]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	85	1			T25	1		T31	1		T47	1
auto[1]	auto_req_mode	92	1			T10	1		T14	1		T15	1
auto[1]	sw_mode	853	1			T2	1		T73	1		T6	3
auto[2]	boot_req_mode	2	1			T339	1		T340	1		-	-
auto[2]	auto_req_mode	4	1			T341	1		T342	1		T343	1
auto[2]	sw_mode	76	1			T1	1		T330	1		T81	1
auto[3]	boot_req_mode	2	1			T344	1		T345	1		-	-
auto[3]	auto_req_mode	3	1			T332	1		T346	1		T347	1
auto[3]	sw_mode	71	1			T263	3		T331	1		T348	1
auto[4]	boot_req_mode	2	1			T335	1		T349	1		-	-
auto[4]	auto_req_mode	1	1			T350	1		-	-		-	-
auto[4]	sw_mode	20	1			T333	11		T334	3		T351	1
auto[5]	boot_req_mode	1	1			T337	1		-	-		-	-
auto[5]	auto_req_mode	1	1			T352	1		-	-		-	-
auto[5]	sw_mode	18	1			T231	14		T336	1		T353	1
auto[6]	auto_req_mode	4	1			T354	1		T355	1		T356	1
auto[6]	sw_mode	124	1			T86	1		T83	1		T338	13
auto[7]	boot_req_mode	31	1			T30	1		T82	1		T357	1
auto[7]	auto_req_mode	38	1			T53	1		T113	1		T11	1
auto[7]	sw_mode	730	1			T3	1		T26	1		T28	11